Volatile Memory Bit Flip Detection Using Column Counters
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Solution Overview
Problem
Volatile memory devices face challenges in efficiently detecting and correcting bit flips, which can lead to data errors due to interference or power noise, without incurring significant overhead in resources or complexity.
Innovation Solution
A volatile memory device with a memory cell array, counter group, calculator, and control circuit that performs error detection and correction by comparing data before and after write operations, using error detection codes to identify bit flips and update counters, allowing for targeted correction with minimal overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional error detection and correction methods are used, then data integrity is improved, but device complexity and overhead increase
Solution Approach 1:
The patent divides the error detection and correction function into separate modules: counter groups for each column that track data changes, and a calculator that processes EDC check results. This segmentation allows each component to perform a specific function efficiently, reducing overall system complexity while maintaining reliability.
Solution Approach 2:
The patent implements preliminary action by maintaining count values in counter groups that reflect the state of memory cells before write operations. When a bit flip is detected through EDC check, the pre-maintained count values enable rapid identification of the affected column without requiring complex analysis, thus reducing overhead.
2Measurement precision
If comprehensive error checking is performed on all memory cells, then detection precision is improved, but loss of time increases
Solution Approach 1:
The patent applies local quality by focusing error detection efforts only on columns where bit flips are likely to occur. The calculator compares EDC check results with count values from counter groups to identify specific columns with errors, rather than uniformly checking all memory cells. This localized approach maintains detection precision while significantly reducing the time required.
Solution Approach 2:
The patent replaces comprehensive mechanical scanning of all memory cells with a computational approach using EDC checks and counter value comparisons. The calculator efficiently identifies error locations by mathematical comparison rather than physical inspection, reducing checking time while maintaining precision.
3Reliability
If error correction is implemented, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent implements self-service error correction where the memory system automatically detects and corrects bit flips without external intervention. The counter groups and calculator work together to identify errors, and the control circuit automatically performs correction by flipping the identified bit, eliminating the need for complex external error correction mechanisms.
Solution Approach 2:
The patent merges the error detection and correction functions into a unified system where the same counter groups and calculator used for detection also facilitate correction. The control circuit integrates both functions by using the identified error locations from the calculator to directly perform the correction operation, simplifying the overall device structure.
Data Source
AI summary
A volatile memory device includes memory cells arranged on rows and columns; first counters each storing a count value representing a number of cells in which first data is stored among cells of a corresponding column, wherein the count value is updated or maintained whenever a write operation on each of the rows is performed; a calculator calculating a number of cells in which the first data is stored for each of the columns upon a determination that an EDC check on any one row among the rows fails, and determining a column in which a bit flip occurs by comparing the calculated number and the count value for each of the columns; and a control circuit determining that a cell of the row on which the EDC check fails among cells of the column in which the bit flip occurs is the bit-flipped cell.