Volatile Non-Volatile Memory Array Design for Fast Access
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Solution Overview
Problem
Existing non-volatile memory arrays face challenges with high access times and surface area usage due to slow read and write operations of resistive elements, leading to increased power consumption.
Innovation Solution
A memory array design incorporating volatile and non-volatile memory cells, where non-volatile memory cells are coupled with resistive elements programmable by current direction, and a control circuit activates transistors to program and read resistive states, reducing the need for a dedicated write circuit and allowing for a common read/write circuit, thus minimizing transistor count and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If resistive elements are used for non-volatile data storage, then data can be stored non-volatily, but read and write operations become slow resulting in high access time
Solution Approach 1:
The memory cell is segmented into volatile and non-volatile portions, with the volatile portion handling fast read/write operations and the non-volatile portion providing persistent storage. This segmentation allows the system to achieve both fast access times and non-volatile storage capability by operating on different portions for different purposes.
Solution Approach 2:
Data is preliminarily stored in the volatile memory portion which provides fast access, while the non-volatile memory portion serves as a backup that is updated periodically. This preliminary action in the volatile portion eliminates the need to access the slower non-volatile portion for every read/write operation.
2Speed
If a circuit for programming resistive element state and for reading, amplifying and storing programmed state is provided in each memory cell, then access times improve, but surface used by each memory cell and power consumption increase
Solution Approach 1:
The volatile and non-volatile memory cells are merged into a single integrated structure where they share common bit lines and control circuits. This merging eliminates the need for separate read/write circuits for each portion, reducing the overall surface area while maintaining fast access times through the volatile portion.
Solution Approach 2:
The memory cell structure is designed to be universal, with the volatile and non-volatile portions sharing common control and signal lines. This multi-functionality allows the same circuit infrastructure to serve both fast access operations and persistent storage, reducing redundant circuitry and surface area.
3Speed
If a circuit for programming resistive element state and for reading, amplifying and storing programmed state is provided in each memory cell, then access times improve, but power consumption increases
Solution Approach 1:
The memory system is segmented into volatile and non-volatile portions, allowing power management strategies where the volatile portion can be powered down when not in use while maintaining data in the non-volatile portion. This segmentation reduces average power consumption while maintaining fast access capability when needed.
Solution Approach 2:
Instead of continuously powering and accessing the full memory circuitry, the system uses periodic actions where data is transferred between volatile and non-volatile portions at appropriate intervals. This allows the high-power volatile portion to remain inactive most of the time, reducing overall power consumption while maintaining fast access capability when required.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design achieves faster access times and reduced area usage while maintaining non-volatile data storage, improving efficiency and power management in memory arrays.
Implementation Method 1
programmable resistive elements in memory cells to ensure non-volatile data storage. Such resistive elements are programmable to assume one of two different resistive states. The programmed resistive state is maintained even when a memory cell supply voltage is disconnected
Implementation Method 2
An example of such a current-programmable resistive element is an STT (spin transfer torque) element, which is based on magnetic tunnel junctions (MTJs)
Data Source
Figure 1~3
Figure 4~5
Figure 6~7A
AI summary
The invention relates to a memory array comprising: a first volatile memory cell (202) including first and second cross-coupled inverters (206, 208) between first and second storage nodes (210, 212); a first non-volatile memory cell (204) including at least one resistive element (218, 218A, 218B) that can be programmed to take one of at least two resistive states (Rmin, Rmax); and a control circuit (224) adapted to couple the first non-volatile memory cell to the first and second storage nodes in order to generate a current for programming the resistive state of the at least one resistive element.