Low Offset Voltage Controlled Current Source Using Clock Signal Calibration

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Solution Overview

Problem

Voltage controlled current sources face issues with input offset errors due to operational amplifier limitations, particularly in applications like LED drivers, where high power MOSFETs may not be available, and BJTs are restricted by CMOS process limitations, leading to accuracy and temperature-related issues.

Innovation Solution

A voltage controlled current source system that includes a clock signal generator, operational amplifier, input offset eliminator, sampling and holding circuit, and output circuit, which uses a square-waveform control signal to actively eliminate input offset and store energy for fast response, reducing output errors and improving slew rate.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If high power MOSFETs or BJTs are used to form input differential pair to reduce input offset, then input offset is decreased, but device complexity and manufacturing cost increase

Engineering Contradiction:
Improveinput offsetVSAvoiddevice complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by performing offset calibration before normal operation. The offset eliminator circuit pre-compensates for the operational amplifier's input offset voltage through a calibration phase, eliminating the need for complex high-power MOSFET or BJT differential pairs. This preliminary offset elimination allows the use of standard CMOS operational amplifiers while achieving low offset performance.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces an intermediary offset eliminator circuit that mediates between the operational amplifier and the rest of the system. This intermediary circuit includes calibration switches and compensating components that actively cancel the input offset voltage, allowing standard operational amplifiers to achieve precision comparable to complex differential pair implementations.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Measurement precision

If high power MOSFETs are used to reduce input offset, then input offset is decreased, but response speed becomes slower

Engineering Contradiction:
Improveinput offsetVSAvoidresponse speed
Core Design Contradiction:
Measurement precisionVSSpeed

Solution Approach 1:

The offset calibration is performed preliminarily before the operational amplifier needs to respond to signal changes. By pre-compensating for offset during a calibration phase, the operational amplifier can operate at full speed during normal operation without being burdened by offset correction, thus achieving both low offset and fast response.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements periodic offset calibration where the offset eliminator circuit periodically compensates for drift while allowing the operational amplifier to maintain high-speed operation between calibration cycles. This periodic action separates the slow offset correction process from the fast signal processing, enabling both low offset and high response speed.

Inventive Principle:
Principle #19Periodic action

3Device complexity

If conventional operational amplifiers are used, then device complexity is reduced, but output error increases due to input offset

Engineering Contradiction:
Improvedevice complexityVSAvoidoutput error
Core Design Contradiction:
Device complexityVSMeasurement precision

Solution Approach 1:

The offset eliminator circuit uses feedback mechanisms to detect and compensate for the operational amplifier's input offset voltage. During calibration, the circuit feeds back compensating voltages through switches and compensating components to nullify the offset, allowing conventional operational amplifiers to achieve high precision output without increased device complexity.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The system performs self-service offset calibration where the offset eliminator circuit automatically detects and corrects its own operational amplifier's offset without external intervention. This self-calibrating mechanism maintains high precision using conventional operational amplifiers while keeping the overall system complexity low.

Inventive Principle:
Principle #25Self-service

4Ease of manufacture

If standard CMOS process is used, then manufacturing cost is reduced, but input offset is influenced by temperature and radiation

Engineering Contradiction:
Improvemanufacturing costVSAvoidtemperature stability
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent implements periodic offset calibration that compensates for temperature-induced offset drift. The offset eliminator circuit periodically re-calibrates the operational amplifier to account for temperature changes, maintaining precision despite using standard CMOS process components that are sensitive to temperature and radiation effects.

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS8710819B2Low offset, fast response voltage controlled current source and controlling method thereof
Publication Date: 2014.04.29 SILERGY SEMICON TECH (HANGZHOU) CO LTD
  • US8710819B2 patent drawing
  • US8710819B2 patent drawing
  • US8710819B2 patent drawing

AI summary

The present invention relates to a low offset and fast response voltage controlled current source, controlling method, and a power supply thereof. In one embodiment, a voltage controlled current source can include: a clock signal generator, a first operational amplifier, an input offset eliminator, a sampling and holding circuit, and an output circuit. The input offset eliminator can receive a clock signal, an input voltage, and a feedback voltage, and can (i) store and then eliminate an input offset of the first operation amplifier, and generate an error signal in accordance with an error between the input and feedback voltages when the clock signal is active, and (ii) generate the error signal in accordance with the stored input offset and the error between the input and feedback voltages when the clock signal is inactive.