On-Die Voltage Regulator Debugging via Shared Pin Multiplexing
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Solution Overview
Problem
Debugging on-die voltage regulators (VRs) integrated into System-on-Chip (SoC) is challenging due to the absence of dedicated pins, making it costly and complex, especially when multiple VRs are present, as existing methods require separate pins for monitoring and debugging, which is not feasible economically or practically.
Innovation Solution
The use of shared pins, analog and digital multiplexers, fuse signal overriding, and finite state machine (FSM) control to debug on-die VRs, allowing for monitoring and optimization of VR performance without the need for dedicated pins, by employing multiplexers to select and override signals, and adjusting reference voltages to determine optimal trim settings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dedicated pins are used for monitoring VR characteristics, then debugging capability is improved, but device complexity and cost increase
Solution Approach 1:
The patent applies universality by enabling general-purpose I/O pins to serve dual functions: normal operational I/O functions and VR debugging/monitoring functions. The multiplexer routes VR monitoring signals to these general pins, allowing them to universally handle both regular I/O tasks and specialized VR characterization without requiring dedicated pins.
Solution Approach 2:
The patent introduces a multiplexer as an intermediary component that mediates between the VR monitoring circuitry and the general-purpose I/O pins. This intermediary enables signal routing flexibility, allowing VR characteristics to be monitored through existing pins while maintaining their normal functions, thus avoiding the need for dedicated debugging pins.
2Measurement precision
If separate pins are provided for each on-die VR, then debugging precision is improved, but manufacturing cost increases
Solution Approach 1:
The patent merges multiple VR monitoring functions into shared I/O pins through the use of multiplexers. Instead of providing separate pins for each VR, the system combines monitoring capabilities for multiple VRs into a smaller set of general-purpose pins, reducing pin count and manufacturing complexity while maintaining the ability to precisely monitor each individual VR when needed.
Solution Approach 2:
The patent implements dynamic signal routing through multiplexers that can switch between different VR monitoring signals and general I/O functions. This dynamic capability allows the same pin to serve different purposes at different times, enabling precise monitoring of individual VRs when required while reducing the overall pin count and manufacturing cost.
3Productivity
If multiple on-die VRs are integrated, then power management efficiency is improved, but debugging difficulty increases
Solution Approach 1:
The patent introduces multiplexers as intermediary components that manage the complexity of monitoring multiple on-die VRs. These multiplexers selectively route monitoring signals from multiple VRs to shared I/O pins, providing a systematic approach to debugging that scales with the number of VRs without proportionally increasing debugging difficulty.
Solution Approach 2:
The patent applies universality by designing a debugging architecture where general-purpose I/O pins can monitor multiple different VRs through multiplexing. This universal approach allows the same debugging infrastructure to handle any number of on-die VRs, maintaining manageable debugging complexity even as power management efficiency improves through higher VR integration.
Data Source
AI summary
Described is an apparatus which comprises: a first voltage regulator (VR) having a reference input node; and a first multiplexer to provide a reference voltage to the reference input node and operable to select one of at least two different reference voltages as the reference voltage.