On-Die Voltage Regulator Debugging via Shared Pin Multiplexing
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Solution Overview
Problem
Debugging on-die voltage regulators (VRs) integrated into System-on-Chip (SoC) is challenging due to the absence of dedicated pins, making it costly and complex, especially when multiple VRs are present, as existing methods require expensive pin provisioning for monitoring and testing.
Innovation Solution
The use of shared processor pins, analog and digital multiplexers, fuse signal overriding, and finite state machine (FSM) control to debug on-die VRs, allowing for optimized trim settings and monitoring of output voltages, enabling debugging without the need for separate pins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Difficulty of detecting and measuring
If dedicated pins are provided on SoC for monitoring VR characteristics, then debugging capability is improved, but manufacturing cost increases
Solution Approach 1:
The patent makes existing processor pins serve dual purposes: normal processor I/O functions and VR debugging/monitoring functions. The pins are configured to monitor VR output voltages and characteristics during both operational and debug modes, eliminating the need for dedicated debugging pins and reducing manufacturing costs while maintaining full debugging capability.
Solution Approach 2:
The VR debugging system uses the processor's own existing pin infrastructure to monitor and debug the VR characteristics. Instead of requiring external dedicated debugging pins, the processor leverages its own pin resources to perform self-diagnosis and monitoring of the integrated VR, reducing external dependencies and manufacturing complexity.
2Measurement precision
If separate pins are provided for each on-die VR, then debugging precision is improved, but device complexity increases
Solution Approach 1:
The patent implements a universal pin monitoring approach where a single pin or shared pin infrastructure can monitor multiple on-die VRs by selectively configuring which VR output is routed to the monitoring pin. This is achieved through multiplexing capabilities that allow the same physical pin to observe different VR outputs at different times, maintaining measurement precision while reducing pin count and complexity.
Solution Approach 2:
The patent segments the monitoring function by implementing selective routing capabilities that allow different VR outputs to be monitored through shared pins at different time intervals. The system divides the monitoring task into sequential phases where each VR can be individually monitored through the shared pin infrastructure, maintaining debugging precision without requiring dedicated pins for each VR.
3Power
If multiple on-die VRs are integrated, then power performance is improved, but debugging difficulty increases
Solution Approach 1:
The patent implements periodic monitoring of multiple VRs through shared pins by sequentially switching between different VR outputs at defined time intervals. The system periodically routes the output of different VRs to the shared monitoring pin, allowing comprehensive monitoring of all VRs over time while maintaining the power performance benefits of multiple integrated VRs. This time-division multiplexing approach makes debugging manageable despite the presence of multiple VRs.
Solution Approach 2:
The patent introduces dynamic configuration capabilities where the pin routing and monitoring parameters can be changed in real-time based on which VR is currently being monitored. The system dynamically switches the monitoring target between multiple VRs and can adjust monitoring frequency and parameters adaptively, enabling effective debugging of multiple VRs without compromising their power performance or requiring static dedicated pins for each VR.
Data Source
AI summary
Described is an apparatus which comprises: a first voltage regulator (VR) having a reference input node; and a first multiplexer to provide a reference voltage to the reference input node and operable to select one of at least two different reference voltages as the reference voltage.