Programmable Voltage Regulator Scan Shift Control
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Solution Overview
Problem
Current integrated circuit testing techniques face challenges in critical path timing testing due to failures in the shift portion of scan tests, particularly at different temperatures, which require multiple oven insertions and are hampered by temperature inversion effects in sub 65 nm processes, making defect analysis and debug difficult.
Innovation Solution
Implementing a programmable voltage regulator to adjust supply voltages during scan testing, allowing for different voltages during shift and capture phases, thereby simulating temperature testing without the need for multiple temperature insertions, and reducing stress on scan paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If temperature testing is performed using multiple oven insertions, then critical path timing testing at different temperatures is achieved, but device complexity and testing time increase
Solution Approach 1:
The patent changes the voltage parameter supplied to the device under test during scan testing to simulate different temperature conditions. By adjusting the voltage from a first voltage during shift operations to a second voltage during capture operations, the system can test critical path timing without physical temperature changes, thereby avoiding multiple oven insertions and reducing testing system complexity
Solution Approach 2:
The patent creates a virtual temperature effect by copying the impact of temperature changes through voltage modulation. Instead of physically heating or cooling the device, the system applies voltage adjustments that produce equivalent timing effects, allowing temperature-related timing tests to be performed without actual temperature changes
2Reliability
If voltage is increased during shift operations, then scan path timing margin is improved, but power consumption increases
Solution Approach 1:
The patent dynamically adjusts the voltage supplied to the device under test based on the operational phase. The voltage is increased during shift operations to improve scan path timing reliability, then reduced during capture operations to lower power consumption. This dynamic voltage adjustment allows the system to optimize for reliability when needed and for energy efficiency at other times
Solution Approach 2:
The patent applies periodic voltage adjustments that correlate with the scanning and capturing cycles. Voltage is periodically increased during shift portions and decreased during capture portions, creating a rhythmic pattern of power consumption that aligns with the testing phases, thereby improving reliability during critical scan operations while managing overall power usage
3Measurement precision
If multiple voltage levels are applied during capture operations, then timing analysis accuracy is improved, but device complexity increases
Solution Approach 1:
The patent segments the capture operation into multiple portions, each with its own voltage level. A first voltage is applied during a first portion of capture operations, and a second voltage is applied during a second portion. This segmentation allows timing analysis at multiple voltage points without requiring a fully complex multi-voltage system, as the voltage changes are tied to specific operational segments
Data Source
AI summary
During scan testing a voltage regulator is programmed to supply a first voltage to logic under test during a shift portion of the scan test, a second voltage during a first portion of a capture portion of the scan test and at least a third voltage during a second portion of the capture portion of the scan test. The availability of a programmable voltage regulator during shift and capture portions of scan testing allows a less stressful voltage to be used during a shift portion of the scan test to reduce shift failures and allows various voltages to be used during capture portions of the scan testing as a surrogate for testing at different temperatures and to provide more flexibility in testing margins.