Integrated Voltage Level Shifter Latch for Faster Switching
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Solution Overview
Problem
Conventional voltage level shifter devices face challenges in efficiently shifting voltage levels between digital and analog portions of integrated circuits due to conflicts between NMOS and PMOS transistors, leading to poor transconductance, substantial parasitic capacitances, and limited frequency performance, which requires large transistor sizes and area consumption.
Innovation Solution
The proposed solution involves using PMOS transistors connected as diodes in the latch circuit, along with small, high-performance transistors, to weaken the latch and allow for efficient switching without oversizing the input stage, thereby balancing the conductance of NMOS and PMOS transistors and reducing parasitic capacitances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If NMOS transistors are designed with much higher W/L size ratio than PMOS transistors to drive output voltage strongly towards GND, then the voltage shifting capability is improved, but the area occupied by transistors increases substantially
Solution Approach 1:
The patent changes the threshold voltage parameter of NMOS transistors by using specialized devices (such as strained silicon or junctionless transistors) that can withstand VCC voltage while maintaining lower threshold voltage. This allows NMOS transistors to achieve strong drive capability without requiring excessive W/L size ratios, thereby reducing the occupied area while maintaining voltage shifting capability.
2Power
If NMOS transistors with lower threshold voltage are used to withstand VCC voltage, then the voltage shifting capability is improved, but the transistor area increases and isolation from substrate becomes difficult
Solution Approach 1:
The patent employs specialized NMOS transistor structures that are optimized for this specific application of withstanding VCC voltage while providing low threshold voltage. These specialized transistors accept the trade-off of larger area as a necessary cost to achieve the required voltage handling capability and low threshold voltage performance.
3Stability of the object's composition
If conventional transistor sizes are used in the latch circuit, then the circuit is stable, but switching speed is limited due to conflict between NMOS and PMOS transistors
Solution Approach 1:
The patent introduces dynamic control mechanisms that temporarily reduce the strength of PMOS transistors during switching transitions. This is achieved through additional control gates or body biasing that dynamically adjust the PMOS conductance, allowing NMOS transistors to quickly override the latch state when needed, thereby improving switching speed while maintaining stability during steady-state operation.
Data Source
AI summary
A voltage level shifter device an input stage and an output stage. The input stage is configured to lower one of the first and second output terminals to the low level according to the level of the input voltage. A latch circuit includes a first branch having a first PMOS transistor and a second PMOS transistor coupled in series coupled between a shifted-high-level voltage supply terminal and the first output terminal and a second branch having a third PMOS transistor an a fourth PMOS transistor coupled in series between the shifted-high-level voltage supply terminal and the second output terminal. The first output terminal is a gate of the second PMOS transistor and to a gate of the third PMOS transistor. The second output terminal is coupled a gate of the fourth PMOS transistor and to a gate of the first PMOS transistor.