Voronoi Diagrams for IC Yield Estimation
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Solution Overview
Problem
Current integrated circuit design methods face challenges in quantitatively assessing tradeoffs between design rules to optimize yield, as they often rely on prioritization or designer intuition, which may not result in the best yield improvements.
Innovation Solution
The method employs Voronoi diagrams to compute failure probabilities based on geometric parameters, allowing for visual differentiation and directional displacement of layout edges to decrease failure probability, using pre-computed data for edge orientation and spacing, and incorporates a Yield Tradeoff Assessor (YTA) to assess and visualize these probabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If quantitative yield assessment methods are implemented, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent segments the complex yield assessment problem into manageable parts by dividing the layout into Voronoi regions based on edge proximity. Each region is independently analyzed for its contribution to yield loss, allowing the overall complex computation to be broken down into simpler regional assessments that can be processed more efficiently
Solution Approach 2:
The patent introduces Voronoi diagrams as an intermediary computational structure that mediates between the raw layout geometry and the yield assessment. This intermediary representation simplifies the computation by providing a structured way to identify and analyze critical edge pairs that contribute most to yield loss, avoiding the need for exhaustive analysis of all possible edge interactions
2Reliability
If comprehensive design rule analysis is performed, then reliability is improved, but ease of operation deteriorates
Solution Approach 1:
The patent applies local quality by providing spatially-resolved yield assessment information through Voronoi region analysis. Instead of giving a single overall yield metric, the method identifies specific regions and edge pairs that contribute most to yield loss, allowing designers to focus their optimization efforts on localized areas rather than having to evaluate entire layouts uniformly
Solution Approach 2:
The patent employs visual encoding (color changes) to represent different yield loss contributions and risk levels in the layout. By coloring Voronoi regions or edge segments according to their yield impact, the system transforms complex quantitative data into intuitive visual information that is easy for designers to interpret and act upon
Data Source
AI summary
A method for implementing integrated circuit yield estimation includes computing Voronoi regions for an original integrated circuit layout; for each bisector segment of the Voronoi regions and one or more failure mechanisms, computing a failure probability based on geometric parameters of corresponding Voronoi edge regions associated with the bisector segment, using pre-computed failure probabilities as a function of edge orientation and spacing for the failure mechanisms; for each segment of a design edge bounded by bisectors, computing a change in the failure probability based on the geometric parameters of the Voronoi regions, using pre-computed change in failure probabilities for the failure mechanisms; encoding the computed failure probabilities for each Voronoi region in a manner suitable for visual differentiation by a user; and encoding the computed change in failure probabilities by directional displacement of a layout edge segment that would result in a decrease in failure probability.