Voting Circuit With Self-Correcting Latches for SEU-Hardened TMR
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Solution Overview
Problem
Triple modular redundancy (TMR) circuits in programmable integrated circuits face challenges in mitigating single event upsets (SEUs) caused by atmospheric radiation, which can lead to errors in configuration and logic upsets, requiring efficient voting circuits to ensure correct output.
Innovation Solution
The implementation of a voting circuit arrangement with pull-up and pull-down circuits connected to output nodes, coupled with transmission gates and a control circuit, allowing for self-correction of latches and reducing transistor count from 18 to 4, enabling efficient error correction and minimizing transistor usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional voting circuit is implemented to mitigate single event upsets in TMR circuits, then reliability is improved, but transistor count increases
Solution Approach 1:
The patent combines the voting circuit functionality with the latch circuits by sharing transistors between them. The pull-up and pull-down circuits are merged with the latch structures, allowing the same transistors to serve dual purposes in both voting and latch operations, thereby reducing the total transistor count from 18 to 4 while maintaining TMR reliability
Solution Approach 2:
The transistors in the voting circuit are designed to perform multiple functions: they operate as part of the voting logic during normal operation and as part of the latch structure during state maintenance. This multi-functionality allows a single set of transistors to replace what would traditionally require separate voting and latch components
2Device complexity
If transistor count is reduced in voting circuits, then device complexity is reduced, but self-correction capability may be compromised
Solution Approach 1:
The self-correction capability is maintained by merging the voting circuit pull-up/pull-down mechanisms with the latch reset/set structures. The same transistors that perform voting functions also provide the corrective action when a latch experiences a single event upset, ensuring self-correction without adding separate correction circuitry
Data Source
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AI summary
The disclosed voting circuit includes a pull-up circuit (110) connected to an output node (126) and to a positive supply voltage (122). A pull-down circuit (112) is connected to the output node (126) and to ground (124), and the output node (126) is coupled to receive true output of a first bi-stable circuit (104). The pull-up circuit (1 10) pulls the output node (126) to the positive supply voltage in response to complementary output signals from second (106) and third (108) bistable circuits being in a first state, and the pull-down circuit (1 12) pulls the output node (126) to ground (124) in response to complementary output signals from second (106) and third (108) bi-stable circuits being in a second state that is opposite the first state.