Voting Interlocked Logic Cell Layout for Radiation Soft Error Immunity
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Solution Overview
Problem
Existing sequential logic cells in CMOS technology are vulnerable to soft errors caused by radiation, and certain semiconductor technologies impose design constraints that make it difficult to implement error-reducing layouts like LEAP, limiting their effectiveness.
Innovation Solution
A new sequential logic cell design that connects n-type and p-type MOSFETs in a unique configuration, allowing for a Voting Interlocked Cell (VICE) structure with a majority vote mechanism, which can be implemented using the LEAP technique even in technologies where traditional DICE circuits cannot, and features a layout that reduces or eliminates soft errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional DICE circuit layout is used, then soft error immunity is improved, but design constraints in certain semiconductor technologies make it difficult to implement
Solution Approach 1:
The circuit is divided into two groups of storage nodes (first group and second group) with interlocked connections between them. This segmentation allows the LEAP layout technique to be applied by positioning nodes from different groups in specific spatial relationships, thereby achieving soft error immunity without being constrained by technology-specific design rules that limit traditional DICE implementations.
Solution Approach 2:
The Voting Interlocked Cell circuit serves multiple functions: it operates as a sequential logic element for data storage, implements a majority vote mechanism for error detection and correction, and provides a universal layout structure that can be implemented across different semiconductor technologies without being restricted by specific design constraints. This multi-functionality resolves the contradiction between reliability and ease of manufacture.
2Reliability
If Voting Interlocked Cell structure with majority vote mechanism is implemented, then soft error immunity is enhanced, but circuit complexity increases
Solution Approach 1:
The circuit merges data storage functionality with majority vote error correction functionality into a single integrated structure. The interlocked connection between the two groups of storage nodes simultaneously achieves both data latching and error detection/correction, reducing overall circuit complexity compared to separate implementations of these functions.
Solution Approach 2:
The circuit applies different connection topologies to different groups of storage nodes (first group with first topology, second group with second topology), where each group is optimized for its specific function while contributing to the overall majority vote mechanism. This local differentiation allows the circuit to achieve enhanced reliability without uniformly increasing complexity throughout the entire structure.
Data Source
AI summary
This invention comprises an integrated circuit in CMOS technology which can act as a regular sequential logic latch, having one data signal input, or as a voting latch, having three data signal inputs. The circuit schematic of this integrated circuit is such that it allows for a certain placement of the devices in the physical, manufactured integrated circuit that makes it possible to optimize the arrangement of the n-type MOSFET devices and p-type MOSFET devices in the circuit independently, using the Layout Optimization through Error Aware Positioning (LEAP), and thereby to remove, or reduce, the occurrence of radiation generated soft errors.