VSDM Substrate Warpage Control via Asymmetric Stackup
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Solution Overview
Problem
The incorporation of voltage switchable dielectric materials (VSDM) into printed circuit boards (PCBs) often leads to warpage due to thermal and elastic property mismatches, causing dimensional control issues and loss of planarity during processing.
Innovation Solution
Incorporating a balance region with similar thermal, elastic, or mechanical properties into the PCB design to counteract the effects of the VSDM, which may include additional prepreg layers or materials, and adjusting the stackup structure to maintain balance and symmetry, even if the PCB does not display mirror symmetry with respect to a centerline.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If voltage switchable dielectric materials are incorporated into PCB to provide ESD protection, then reliability is improved, but manufacturing precision deteriorates due to warpage and loss of planarity
Solution Approach 1:
The patent applies asymmetry by intentionally creating an unbalanced PCB stackup design where the VSDM layer is positioned off-center relative to the neutral axis. This asymmetric configuration allows the VSDM to provide ESD protection while the unequal distribution of materials above and below the VSDM layer creates compensating stresses that counteract warpage, thereby maintaining dimensional control despite the presence of the dielectric material with mismatched thermal and elastic properties
Solution Approach 2:
The patent employs parameter changes by carefully selecting and adjusting the thickness, material properties, and stacking sequence of prepreg layers and copper traces surrounding the VSDM layer. By modifying these parameters, the design compensates for the thermal expansion mismatch and elastic modulus differences between the VSDM and surrounding materials, reducing warpage and maintaining planarity during processing
2Reliability
If VSDM layer is added to PCB substrate, then ESD protection is improved, but shape deteriorates due to warpage and bending
Solution Approach 1:
The patent applies the counterweight principle by positioning and dimensioning the prepreg layers and copper traces above and below the VSDM layer to create compensating forces that counteract the warpage induced by the VSDM. The unbalanced stackup is deliberately designed so that the greater thickness of material on one side of the VSDM layer creates a counteracting moment that offsets the bending tendency, thereby maintaining the PCB's flatness and planarity
3Manufacturing precision
If conventional balanced stackup is used for PCB, then manufacturing precision is maintained, but adaptability deteriorates when incorporating VSDM layers
Solution Approach 1:
The patent applies segmentation by dividing the PCB stackup into distinct functional regions: a VSDM-containing region for ESD protection and balance regions with conventional prepreg and copper layers for dimensional stability. This segmentation allows the VSDM to be integrated into a specific location without requiring a complete redesign of the entire stackup, enabling adaptable incorporation of ESD protection while maintaining manufacturing precision through the balanced design of surrounding layers
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a balanced, ESD-protected PCB that meets dimensional specifications, such as flatness within industry standards, by minimizing warpage and ensuring planarity, even with thin substrates, thereby improving processing and performance.
Implementation Method 1
voltage switchable dielectric materials (VSDM) ... behave as an insulator at a low voltage, and a conductor at a higher voltage
Implementation Method 2
thermal and elastic property mismatches... A balance region may include a material having a larger coefficient of thermal expansion (CTE) than that of the first region
Implementation Method 3
A balance region may include a material having a shrinkage percentage that substantially matches that of the first region
Data Source
AI summary
Various aspects provide for incorporating a VSDM into a substrate to create an ESD-protected substrate. In some cases, a VSDM is incorporated in a manner that results in the ESD-protected substrate meeting one or more specifications (e.g., thickness, planarity, and the like) for various subsequent processes or applications. Various aspects provide for designing a substrate (e.g., a PCB) incorporating a VSDM, and adjusting one or more aspects of the substrate to design a balanced, ESD-protected substrate. Certain embodiments include molding a substrate having a VSDM layer into a first shape.