Threshold Voltage Modulation Layer for Nanosheet FET Gate Stability
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Solution Overview
Problem
As semiconductor devices continue to scale down, the reduced separation distance between vertically stacked nanostructures in NS FETs leads to challenges in forming and performing metal gate stacks, including unstable threshold voltage due to metal gate boundary diffusion between WFM layers of n-type and p-type FETs.
Innovation Solution
The implementation of a threshold voltage modulation layer wrapping around each channel layer in NS NFETs, allowing for the same work function metal layers to be used for both NS NFETs and NS PFETs, thereby avoiding complex patterning processes and metal gate boundary diffusion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If separation distance between active device regions is reduced to meet design requirements of smaller technology nodes, then device density and production efficiency are improved, but threshold voltage stability deteriorates due to metal gate boundary diffusion
Solution Approach 1:
A threshold voltage modulation layer is introduced as an intermediary component between the channel layer and the metal gate stack. This modulation layer acts as a mediator that enables independent threshold voltage control for n-type and p-type FETs without requiring separate work function metal layers, thereby maintaining threshold voltage stability even when separation distances are reduced for higher device density.
Solution Approach 2:
The gate structure is segmented into distinct functional layers: the channel layer, the threshold voltage modulation layer, and the metal gate stack. This segmentation allows the modulation layer to be independently optimized for threshold voltage control while the metal gate stack provides uniform work function characteristics, resolving the conflict between device density and threshold voltage stability.
2Adaptability or versatility
If different work function metal layers are used for n-type and p-type FETs to control threshold voltage, then threshold voltage tuning capability is improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The threshold voltage control function is extracted from the work function metal layers and transferred to a dedicated threshold voltage modulation layer. This allows both n-type and p-type FETs to use the same work function metal material, eliminating the need for complex selective patterning processes while maintaining full threshold voltage tuning capability through modulation layer thickness control.
Solution Approach 2:
Threshold voltage is controlled by changing the thickness parameter of the modulation layer rather than changing the material composition of multiple metal layers. This single-parameter control approach simplifies the manufacturing process while providing continuous threshold voltage tuning capability across different device types.
3Productivity
If vertically stacked nanostructures are used to increase functional density, then device integration is improved, but metal gate boundary diffusion between adjacent structures increases
Solution Approach 1:
The threshold voltage modulation layer serves as a protective intermediary between adjacent vertically stacked nanostructures. By providing this intermediate layer, metal gate material diffusion between neighboring structures is prevented, allowing higher functional density through closer spacing of stacked devices without suffering from boundary diffusion effects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration provides greater design flexibility in tuning the threshold voltage, reduces metal gate boundary diffusion, and enhances electron and hole mobilities through strain effects, improving overall device performance.
Implementation Method 1
enhances electron and hole mobilities through strain effects
Data Source
AI summary
A method comprises forming a first fin including alternating first channel layers and first sacrificial layers and a second fin including alternating second channel layers and second sacrificial layers, forming a capping layer over the first and the second fin, forming a dummy gate stack over the capping layer, forming source/drain (S/D) features in the first and the second fin, removing the dummy gate stack to form a gate trench, removing the first sacrificial layers and the capping layer over the first fin to form first gaps, removing the capping layer over the second fin and portions of the second sacrificial layers to from second gaps, where remaining portions of the second sacrificial layers and the capping layers form a threshold voltage (Vt) modulation layer, and forming a metal gate stack in the gate trench, the first gaps, and the second gaps.