3D Monolithic VTFET Logic Gates with Shared Fins
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Solution Overview
Problem
Challenges exist in stacking planar field-effect transistors (FETs) due to their two-dimensional nature, limiting the scalability of complementary metal-oxide-semiconductor (CMOS) area, whereas vertical FETs offer a unique structure for direct stacking but require innovative logic gate designs.
Innovation Solution
The development of logic gate designs for stacked vertical transport field-effect transistor (VTFET) devices, including NAND, NOR, and Inverter gates, where top and bottom VTFETs share fins, with specific patterning and contact formation methods to create functional logic gates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If planar FETs are stacked in the vertical direction, then CMOS area scaling is achieved, but the stacking process becomes very challenging due to the two-dimensional nature of planar FETs
Solution Approach 1:
The patent transitions from planar (2D) FET stacking to vertical (3D) FET stacking by changing the dimensional orientation of the transistor channels. Vertical FETs with vertically oriented channels can be directly stacked along the vertical axis, enabling true three-dimensional integration and overcoming the limitations of planar FET stacking that only achieves apparent vertical stacking through layer-by-layer planar integration.
2Ease of manufacture
If vertical FETs are used for direct stacking, then stacking ease is improved, but logic gate design becomes more complex requiring innovative configurations
Solution Approach 1:
The patent merges multiple vertical FETs into shared fin structures where adjacent fins are combined to form common channels. This merging approach allows multiple transistors to share physical infrastructure (fins, gates, source/drain regions), simplifying the logic gate design by reducing the number of discrete components needed while maintaining the vertical stacking advantage.
Solution Approach 2:
The patent creates universal fin structures that can serve multiple functions simultaneously - a single fin can act as a channel for multiple transistors, serve as a shared source or drain region, and participate in different logic gate configurations (NAND, NOR, inverter). This multi-functionality reduces design complexity by providing reusable building blocks for various logic operations.
3Area of stationary object
If top and bottom VTFETs share fins, then device area is reduced, but manufacturing precision requirements increase for proper contact formation
Solution Approach 1:
The patent segments the shared fin structure into distinct functional regions with isolated contact points. By dividing the fin into separate top and bottom sections with dedicated source/drain regions, the design allows independent contact formation at different heights, reducing the precision requirements compared to forming all contacts at a single interface.
Solution Approach 2:
The patent introduces intermediate dielectric layers and isolation structures between the top and bottom VTFETs that share fins. These intermediary elements provide physical separation and electrical isolation, allowing contacts to be formed at different positions along the fin structure without requiring ultra-precise alignment, thus reducing manufacturing precision requirements.
Data Source
AI summary
Logic gate designs (e.g., NAND, NOR, Inverter) for stacked VTFET designs are provided. In one aspect, a logic gate device is provided. The logic gate device includes: at least one top vertical transport field-effect transistor (VTFET1) sharing a fin with at least one bottom VTFET (VTFET2); a power rail connected to a power contact of the logic gate device; and a ground rail, adjacent to the power rail, connected to a ground contact of the logic gate device. A method of forming a logic gate device is also provided.