Wafer-Level Alignment Marks for Accurate Probe Pad Testing
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Solution Overview
Problem
The increasing complexity of integrated circuit packages, which include multiple device dies with different functions, poses challenges in achieving precise alignment and interconnection, particularly due to thermal expansion mismatches and the need for efficient electrical routing, leading to potential warpage and alignment issues during the packaging process.
Innovation Solution
A method is developed to form a reconstructed wafer by encapsulating multiple device dies with a redistribution structure that includes forming top electrical connectors and alignment marks simultaneously, using a Light-To-Heat-Conversion coating for carrier release and die-attach films, and creating interconnect structures with varying dielectric layers and RDLs for efficient electrical routing, while forming alignment marks in the same process as bond and probe pads for improved alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple device dies are packaged in the same package to achieve more functions, then the functionality and complexity of the package is improved, but alignment precision and interconnection reliability deteriorate due to thermal expansion mismatches and warpage
Solution Approach 1:
The package structure is divided into multiple functional modules, each containing device dies with specific functions. This segmentation allows independent optimization of each module's alignment and interconnection, reducing the overall complexity and improving alignment precision while maintaining high functionality.
Solution Approach 2:
The patent employs parameter changes in the form of alignment marks with specific geometric features (e.g., different shapes, sizes, or positions) that enable precise alignment during the packaging process. These parameter changes allow the system to maintain high alignment precision even when packaging multiple different device dies with varying thermal expansion coefficients.
2Adaptability or versatility
If device dies with different functions are interconnected to form a system, then the system functionality is improved, but thermal expansion mismatches cause warpage and alignment issues
Solution Approach 1:
The patent introduces alignment marks as intermediary features that facilitate precise alignment between device dies with different functions. These alignment marks serve as mediators that enable accurate positioning and interconnection, compensating for thermal expansion mismatches and maintaining structural stability during the packaging process.
Solution Approach 2:
The alignment marks are formed in advance during the semiconductor fabrication process, before the packaging stage. This preliminary action ensures that precise alignment features are already in place, enabling accurate positioning of multiple device dies with different thermal expansion coefficients and preventing warpage issues during interconnection.
3Manufacturing precision
If alignment marks are formed in the same process as bond and probe pads, then alignment precision is improved, but process complexity increases
Solution Approach 1:
The patent merges the formation of alignment marks with the existing bond and probe pad fabrication process. By combining these operations into a single integrated process step, the patent achieves high alignment precision without significantly increasing overall process complexity, as the alignment marks are formed using the same lithography and deposition equipment already required for the electrical connectors.
Solution Approach 2:
The alignment marks are designed to serve multiple functions: they provide alignment references for bonding, serve as test structures for process verification, and can be used for subsequent packaging steps. This multi-functionality reduces the need for separate dedicated alignment features, thereby limiting the increase in process complexity while maintaining high alignment precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables better alignment and electrical connectivity among device dies, reduces warpage due to thermal expansion mismatches, and allows for efficient probing and bonding processes, enhancing the overall packaging efficiency and reliability of complex integrated circuit packages.
Implementation Method 1
using a Light-To-Heat-Conversion coating for carrier release and die-attach films
Data Source
AI summary
A method includes forming a reconstructed wafer, which includes placing a plurality of package components over a carrier, forming an interconnect structure over and electrically interconnecting the plurality of package components, forming top electrical connectors over and electrically connecting to the interconnect structure, and forming alignment marks at a same level as the top electrical connectors. Probe pads in the top electrical connectors are probed, and the probing is performed using the alignment marks for aligning to the probe pads. An additional package component is bonded to the reconstructed wafer through solder regions. The solder regions are physically joined to the top electrical connectors.