Semiconductor Wafer Backside Contact Layer for Electrostatic Chuck Holding

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Solution Overview

Problem

Semiconductor wafers with high resistivity silicon substrates experience difficulty in being securely held on electrostatic chucks due to low current generation, leading to potential de-chucking issues during processing, and high resistivity substrates do not significantly improve RF device performance.

Innovation Solution

A contact layer with a resistivity smaller than the supporting substrate is implemented, either through doping or deposition, to enhance current generation between the wafer and the electrostatic chuck, ensuring secure holding and improved RF device performance without damaging the chuck.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If high resistivity silicon substrate is used, then RF device performance is improved, but current generation between wafer and electrostatic chuck is reduced

Engineering Contradiction:
ImproveRF device performanceVSAvoidcurrent generation
Core Design Contradiction:
ReliabilityVSPower

Solution Approach 1:

The contact layer is applied locally on the backside of the wafer, creating a localized region with different electrical properties. This local modification enables secure electrostatic holding without affecting the overall high resistivity characteristics needed for RF performance.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The contact layer acts as an intermediary between the high resistivity substrate and the electrostatic chuck. It mediates the electrical interaction by providing a low resistivity path for current flow during chucking, while the high resistivity substrate maintains RF performance.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Power

If contact layer with low resistivity is added, then current generation and wafer holding are improved, but wafer structure complexity increases

Engineering Contradiction:
Improvecurrent generationVSAvoidwafer structure
Core Design Contradiction:
PowerVSDevice complexity

Solution Approach 1:

The contact layer modifies the electrical parameter (resistivity) of the wafer backside without changing the fundamental wafer structure. This parameter change enables improved electrostatic holding while maintaining structural simplicity.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The contact layer with a resistivity between 50 ohm-cm and 3000 ohm-cm effectively secures the semiconductor wafer on the electrostatic chuck, preventing unintentional de-chucking and enhancing RF device performance by optimizing the coulomb force applied.

Implementation Method 1

high frequency electric power may be applied to the electrodes to enable positive and negative charges to be respectively produced in the semiconductor wafer and a chuck surface of the electrostatic chuck, such that the semiconductor wafer is attracted and held on the chuck surface by the coulomb force between the semiconductor wafer and the electrodes

Methodology Applied
Scientific EffectElectrical conduction: Conduction (electrical)

Implementation Method 2

the semiconductor wafer is attracted and held on the chuck surface by the coulomb force between the semiconductor wafer and the electrodes

Methodology Applied
Scientific EffectCoulomb force: Coulomb's Law

Data Source

PatentUS11682549B2Semiconductor wafer with modified surface and fabrication method thereof
Publication Date: 2023.06.20 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11682549B2 patent drawing
  • US11682549B2 patent drawing
  • US11682549B2 patent drawing

AI summary

A method comprises depositing a mask layer on a front-side surface of a wafer, wherein a portion of the wafer has a first resistivity; with the mask layer in place, performing an ion implantation process on a backside surface of the wafer to implant a resistivity reduction impurity into the wafer through the backside surface of the wafer to lower the first resistivity of the portion of the wafer to a second resistivity; after performing the ion implantation process, removing the mask layer from the front-side surface of the wafer; and forming semiconductor devices on the front-side surface of the wafer.