Wafer Backside Copper Pillar TSV Interconnect
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Solution Overview
Problem
Conventional through-silicon via (TSV) connections face limitations due to the need for large pitch between TSVs, restricting their placement and increasing interconnection complexity, which leads to increased circuit RC delay and power consumption in two-dimensional integrated circuits.
Innovation Solution
A novel backside connection structure is introduced, featuring a conductive via with a redistribution line on the backside of a semiconductor substrate, a passivation layer with an opening exposing the redistribution line, and a copper pillar electrically connected to it, allowing for improved bondability and increased standoff between stacked dies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional TSV connections are used with large pitch between TSVs, then TSV placement is restricted, but device complexity and interconnection complexity increase
Solution Approach 1:
The patent transitions from conventional 2D TSV placement on the front surface to 3D backside connection structures. By moving the connection interface to the backside of the substrate and using copper pillars extending vertically, the design enables flexible routing in three dimensions, allowing TSVs to be placed more densely without increasing lateral interconnection complexity.
Solution Approach 2:
The connection structure is segmented into distinct functional components: TSVs for vertical penetration, copper pillars for backside exposure and bonding, and redistribution lines for electrical routing. This segmentation allows each component to be optimized independently, with TSVs providing robust vertical connections and copper pillars enabling flexible bond pad placement without constraining TSV pitch.
2Productivity
If more devices are integrated into one chip in 2D, then integration density improves, but the number and lengths of interconnections increase, leading to increased circuit RC delay and power consumption
Solution Approach 1:
By implementing backside connections with copper pillars, the patent reduces the lateral distance that signals must travel across the chip. Vertical TSV connections combined with backside bonding create shorter interconnection paths compared to extended 2D routing, thereby reducing RC delay and power consumption while maintaining high integration density.
3Ease of manufacture
If TSV pitch is increased to allow room for solder balls, then TSV bonding is enabled, but the locations of TSVs are restricted
Solution Approach 1:
Instead of placing solder balls around TSVs on the front surface, the patent inverts the bonding approach by exposing copper pillars on the backside of the substrate. This allows bond pads to be formed on the backside directly over or near TSV openings, eliminating the need for large lateral pitch and enabling flexible TSV placement while maintaining bonding capability.
Data Source
AI summary
An integrated circuit structure includes a semiconductor substrate having a front side and a backside, and a conductive via penetrating the semiconductor substrate. The conductive via includes a back end extending to the backside of the semiconductor substrate. A redistribution line (RDL) is on the backside of the semiconductor substrate and electrically connected to the back end of the conductive via. A passivation layer is over the RDL, with an opening in the passivation layer, wherein a portion of the RDL is exposed through the opening. A copper pillar has a portion in the opening and electrically connected to the RDL.