Wafer Benchmark Circuit for Dense Ring Oscillator Frequency Testing
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Solution Overview
Problem
In semiconductor industries, the limited space on a wafer constrains the measurement of ring oscillator (RO) frequency variations, which is crucial for High-Performance Computing (HPC), Internet of Things (IoT), and other applications, as existing methods require large areas for buffering and adjustment circuits, limiting the number of ROs that can be tested.
Innovation Solution
A benchmark circuit architecture that shares a single buffering circuit and adjustment circuit among multiple ring oscillators, using switching circuits controlled by a D flip flop and a multiplexer to adjust frequencies, allowing for a higher density of ROs on the wafer by reducing the space required for each test line.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a traditional benchmark circuit architecture with separate buffering and adjustment circuits for each ring oscillator is used, then accurate frequency measurement can be achieved, but the wafer area required for testing is large and the number of ROs that can be tested is limited
Solution Approach 1:
The patent merges multiple separate buffering circuits and adjustment circuits into a single shared buffering circuit and a single shared adjustment circuit that serves multiple ring oscillators. This consolidation reduces the total wafer area required for testing while maintaining the ability to accurately measure frequencies of individual ROs through selective switching.
Solution Approach 2:
The shared buffering circuit and adjustment circuit are designed to be universal components that can handle signals from multiple different ring oscillators. The switching circuitry enables these universal components to be dynamically allocated to different ROs, allowing one set of circuits to perform the function of what would traditionally require multiple separate circuit sets.
2Reliability
If more ring oscillators are placed on the wafer to increase measurement opportunities, then process issue detection capability is improved, but the limited wafer space constrains the number of ROs that can be tested
Solution Approach 1:
By merging the buffering and adjustment circuits into shared resources, the patent significantly reduces the space footprint per test line. This space efficiency enables placing up to 200 ring oscillators on a single wafer, compared to the traditional limit of about 4 ROs per wafer, thereby dramatically improving process issue detection capability through statistical sampling.
Solution Approach 2:
The patent segments the testing function into modular components: multiple simple ring oscillators can be densely packed, while the complex buffering and adjustment functions are consolidated into shared resources accessed through switching mechanisms. This segmentation allows high-density RO placement without proportionally increasing the area for support circuits.
3Area of stationary object
If a shared buffering circuit and adjustment circuit are used among multiple ring oscillators, then wafer area is reduced and RO density is increased, but circuit complexity increases due to switching mechanisms
Solution Approach 1:
The patent introduces dynamic switching mechanisms (multiplexers and switches) that allow the static shared buffering and adjustment circuits to be dynamically allocated to different ring oscillators based on testing requirements. This dynamic allocation enables the circuit to adapt its configuration, reducing the need for permanent dedicated connections and thereby reducing overall area despite the added switching complexity.
Data Source
AI summary
The present disclosure provides a semiconductor wafer. The semiconductor wafer includes: a scribe line between a first row of dies and a second row of dies, and a benchmark circuit disposed on the scribe line. The benchmark circuit includes a first switching circuit, a first process control monitoring (PCM) device and a second PCM device coupled to the first switching circuit, and a second switching circuit. The first switching circuit is configured to selectively couple the first PCM device and the second PCM device to receive a test signal, wherein the first PCM device and the second PCM device are configured to output a first output signal and a second output signal in response to the test signal, respectively. The second switching circuit is configured to selectively couple the first PCM device and the second PCM device to output the first output signal or the second output signal.