Wafer Benchmark Circuit for Dense Ring Oscillator Measurement
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Solution Overview
Problem
In semiconductor industries, the limited space on a wafer constrains the measurement of ring oscillator (RO) frequency variations, which is crucial for High-Performance Computing (HPC), Internet of Things (IoT), and other applications, as existing methods require large areas for buffering and adjustment circuits, limiting the number of ROs that can be tested.
Innovation Solution
A benchmark circuit architecture that shares a single buffering circuit and adjustment circuit among multiple ring oscillators, using switching circuits controlled by a D flip flop and a multiplexer to adjust frequencies into a detectable range, allowing for a higher density of ROs on the wafer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If traditional separate buffering and adjustment circuits are used for each ring oscillator, then frequency measurement accuracy is maintained, but wafer space consumption increases significantly
Solution Approach 1:
Multiple ring oscillators share a common buffering circuit and adjustment circuit instead of each having dedicated circuits. The patent implements this by providing a single buffering circuit that receives signals from multiple ROs and a single adjustment circuit that processes signals from the buffering circuit, thereby consolidating previously separate resources into shared infrastructure.
Solution Approach 2:
The buffering circuit and adjustment circuit are designed to handle signals from multiple different ring oscillators, making these circuits universal rather than dedicated to a single RO. The switching circuit enables the same buffering and adjustment resources to be selectively connected to different ROs based on measurement needs.
2Quantity of substance
If more ring oscillators are placed on the wafer, then measurement coverage of process issues increases, but available wafer space decreases
Solution Approach 1:
The patent consolidates buffering and adjustment functions into shared circuits that serve multiple ROs simultaneously, eliminating the need for separate circuits for each oscillator. This merging approach dramatically reduces the space required per RO while maintaining the ability to measure multiple oscillators.
Solution Approach 2:
The measurement system is segmented into modular components: multiple independent ROs can be selectively activated and measured using shared infrastructure. The switching circuit enables selective connection of different RO groups to the common buffering and adjustment circuits, allowing flexible measurement configurations that optimize space utilization.
3Reliability
If dedicated buffering circuits are allocated to each ring oscillator, then signal processing quality is ensured, but device complexity increases
Solution Approach 1:
The patent merges multiple buffering functions into a single buffering circuit that handles signals from multiple ROs. This consolidation reduces the total number of circuits while maintaining signal processing quality through proper switching control that ensures each RO receives appropriate buffering when active.
Solution Approach 2:
The system employs dynamic switching control through the switching circuit, which selectively connects different ROs to the common buffering circuit based on measurement requirements. This dynamic reconfiguration allows the same buffering resources to serve multiple ROs at different times, reducing overall complexity while maintaining signal quality for each measurement.
Data Source
AI summary
The present disclosure provides a semiconductor wafer. The semiconductor wafer includes: a scribe line between a first row of dies and a second row of dies; and a benchmark circuit disposed adjacent to the scribe line and electrically coupled to a first conductive contact and a second conductive contact. The benchmark circuit includes a first device-under-test (DUT); a second DUT; a first switching circuit configured to selectively couple the first DUT and the second DUT to the first conductive contact; and a second switching circuit configured to selectively couple the first DUT and the second DUT to the second conductive contact.