Wafer-Bonded Transistor Stacking for 3D Nanosheet Integration
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Solution Overview
Problem
Existing semiconductor device fabrication techniques face challenges in scaling beyond single digit nanometer nodes due to limitations in two-dimensional circuits, necessitating a transition to three-dimensional transistor stacking without the complexity of epitaxial growth methods.
Innovation Solution
A method involving wafer bonding of semiconductor-on-insulator stacks with etch-selective insulators to form single crystal horizontal nanosheets, enabling 3D transistor integration without SiGe epitaxial layers, and utilizing dielectric bonding for built-in isolation and separate metal gate electrodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional circuits are used to scale transistor density, then manufacturing process complexity is low, but transistor density per unit area reaches a saturation point at single digit nanometer nodes
Solution Approach 1:
The patent transitions from two-dimensional circuit layout to three-dimensional transistor stacking by bonding multiple wafer layers vertically. Each wafer contains semiconductor-on-insulator stacks with transistors arranged in vertical columns, enabling density scaling along the vertical dimension rather than being constrained to planar expansion.
2Device complexity
If epitaxial growth methods are used to form 3D transistor stacks, then vertical integration is achieved, but process complexity and manufacturing difficulty increase significantly
Solution Approach 1:
The patent divides the 3D transistor stack into separate wafer layers that are fabricated independently using conventional planar processes. Each wafer is then bonded to form the vertical stack, segmenting the complex 3D fabrication into manageable 2D steps that can be performed with existing manufacturing capabilities.
Solution Approach 2:
The patent introduces wafer bonding as an intermediary process between conventional fabrication steps. The bonding interface serves as a mediator that joins separately fabricated wafer layers into a unified 3D structure, enabling vertical integration without requiring complex epitaxial growth processes.
3Productivity
If conventional wafer bonding is used to stack wafers, then 3D integration is achieved, but control over transistor alignment and interface quality is difficult
Solution Approach 1:
The patent performs preliminary fabrication of semiconductor-on-insulator stacks on each wafer before bonding. This includes forming insulator layers, semiconductor layers, and transistor structures in advance, so that when wafers are bonded, the structures are already precisely defined and aligned, eliminating the need for post-bonding alignment adjustments.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables increased transistor density in a compact volume by eliminating process steps and achieving high K gate dielectrics and side-by-side device configurations, facilitating easy masking of width/length ratios in 3D integration.
Implementation Method 1
The first dielectric layer and the second dielectric layer include a same dielectric bonding material. The bonding the first dielectric layer to the second dielectric layer includes performing fusion bonding.
Data Source
AI summary
A method of fabricating a semiconductor device includes receiving a first wafer including a first substrate on a backside of the first wafer, and a first semiconductor-on-insulator (SOI) stack on a front side of the first wafer. The first SOI stack includes a first semiconductor. A second wafer is received that includes a second substrate on a backside of the second wafer, and a second SOI stack on a front side of the second wafer. The second SOI stack includes a second semiconductor. The front side of the first wafer is bonded to the front side of the second wafer, via at least one dielectric bonding material, to form a bonded wafer. The second substrate is removed. A stack of transistor devices is formed with the first semiconductor used as a first channel for a first transistor and the second semiconductor used as a second channel for a second transistor.