Wafer Bonding for 3D NOR Memory Thermal Decoupling
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Solution Overview
Problem
The thermal budget constraints in fabricating 3-dimensional NOR memory circuits limit the integration of optimal CMOS devices and interconnect layers, as high temperatures required for memory device fabrication exclude the use of certain materials like copper and aluminum, leading to increased interconnect resistance and signal delays.
Innovation Solution
Wafer bonding techniques are used to separate the fabrication of CMOS devices and interconnect layers from the 3-dimensional NOR memory structure, allowing for the use of lower temperatures and enabling the integration of copper or aluminum interconnects, while also forming single-crystal epitaxial silicon channels for memory transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high temperature fabrication is used for 3-dimensional NOR memory structure, then memory device performance is improved, but interconnect resistance increases and signal delays occur due to exclusion of copper and aluminum materials
Solution Approach 1:
The fabrication process is segmented into two independent parts: memory structure fabrication on a first substrate and CMOS device fabrication on a second substrate. This allows each part to be optimized independently for its specific thermal requirements, resolving the contradiction between high-temperature memory fabrication and low-temperature interconnect material constraints.
Solution Approach 2:
A bonding interface is introduced as an intermediary between the memory structure and CMOS devices. This bonding interface enables thermal decoupling, allowing the memory side to undergo high-temperature processing while the CMOS side with sensitive interconnect materials remains at lower temperatures, thus enabling use of optimal interconnect materials without compromising memory device performance.
2Manufacturing precision
If high temperature processing is applied to fabricate memory devices, then optimal memory structure is achieved, but use of copper and aluminum interconnects is excluded
Solution Approach 1:
The manufacturing process is divided into separate fabrication sequences for memory and CMOS devices on different substrates. This segmentation allows copper or aluminum interconnects to be manufactured on the CMOS substrate at lower temperatures while the memory substrate undergoes high-temperature processing, thus enabling optimal material selection for both.
Solution Approach 2:
The problem is solved by adding a spatial dimension - using separate substrates for memory and CMOS devices. This dimensional separation allows independent temperature control and material optimization in different spatial locations, enabling use of low-resistance interconnect materials without compromising memory structure quality.
3Ease of manufacture
If separate fabrication of CMOS devices and memory structure is performed, then optimal materials for interconnects can be used, but additional wafer bonding steps are required
Solution Approach 1:
The CMOS device fabrication is extracted from the high-temperature memory fabrication process and performed separately on a different substrate. This extraction allows use of optimal interconnect materials that would be incompatible with high-temperature processing, while the additional bonding step integrates the separately fabricated components into a functional unified device.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach decouples the thermal budget constraints of memory devices from CMOS devices and interconnect layers, allowing for improved memory device performance by reducing signal delays and enabling the use of optimal materials for interconnects, and providing a highly efficient memory array with single-crystal epitaxial silicon channels.
Implementation Method 1
two wafers of near-equal area or equal areas are joined, for example, by thermocompression, adhesive, anodic, or thermal techniques
Implementation Method 2
two wafers of near-equal area or equal areas are joined, for example, by thermocompression, adhesive, anodic, or thermal techniques
Implementation Method 3
two wafers of near-equal area or equal areas are joined, for example, by thermocompression, adhesive, anodic, or thermal techniques
Implementation Method 4
two wafers of near-equal area or equal areas are joined, for example, by thermocompression, adhesive, anodic, or thermal techniques
Implementation Method 5
providing a highly efficient memory array with single-crystal epitaxial silicon channels
Data Source
AI summary
A memory array and single-crystal circuitry are provided by wafer bonding (e.g., adhesive wafer bonding or anodic wafer bonding) in the same integrated circuit and interconnected by conductors of a interconnect layer. Additional circuitry or memory arrays may be provided by additional wafer bonds and electrically connected by interconnect layers at the wafer bonding interface. The memory array may include storage or memory transistors having single-crystal epitaxial silicon channel material.