Wafer Bonding Pad Compensation for Overlay Error Correction

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Solution Overview

Problem

Wafer warpage during manufacturing leads to overlay errors in the bonding process of three-dimensional integrated circuits, affecting electrical connections between chips.

Innovation Solution

A compensation method involving overlay checks and adjustments to the positions of conductive pads on wafers using lithography tools and bonders to ensure proper alignment and contact, including separate and re-bonding steps if initial checks exceed predetermined specifications.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If wafer bonding is performed without compensation, then the bonding process is simple and fast, but overlay errors occur due to wafer warpage affecting electrical connections

Engineering Contradiction:
Improveoverlay accuracyVSAvoidbonding process complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent performs overlay checks and compensation actions before the final bonding process. Specifically, a first overlay check is performed on the wafers before bonding, and if errors are detected, a first compensation method is applied to adjust pad positions. This preliminary compensation ensures that when bonding occurs, the overlay accuracy is already corrected, preventing electrical connection failures without requiring complex real-time adjustment mechanisms during bonding.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements a feedback loop where overlay check results directly influence subsequent bonding operations. The system measures actual overlay accuracy through electrical connection tests, compares it against specifications, and automatically triggers compensation methods when errors are detected. This closed-loop feedback mechanism maintains high overlay accuracy without requiring manual intervention or overly complex bonding equipment.

Inventive Principle:
Principle #23Feedback

2Reliability

If overlay checks are performed frequently, then overlay errors are detected early, but manufacturing time increases

Engineering Contradiction:
Improveelectrical connection reliabilityVSAvoidmanufacturing efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent performs overlay checks at specific critical points rather than continuously. A first overlay check is performed before bonding, and a second overlay check is performed after compensation but only when the first check indicates errors. This selective checking approach provides sufficient reliability to detect and correct overlay errors while avoiding the time penalty of excessive or continuous measurements, maintaining manufacturing efficiency.

Inventive Principle:
Principle #16Partial or excessive action

3Manufacturing precision

If compensation methods are applied to adjust pad positions, then contact area between pads is improved, but the number of processing steps increases

Engineering Contradiction:
Improvepad contact areaVSAvoidprocessing cycle time
Core Design Contradiction:
Manufacturing precisionVSProductivity

Solution Approach 1:

The patent applies compensation methods in advance before bonding to counteract anticipated overlay errors. When the first overlay check detects errors, the first compensation method adjusts pad positions beforehand, ensuring adequate contact area during bonding. This preliminary correction prevents bonding failures without requiring rework or additional steps after bonding, thus maintaining processing efficiency while improving pad contact quality.

Inventive Principle:
Principle #9Preliminary anti-action

Data Source

PatentUS12588574B2Compensation method for wafer bonding
Publication Date: 2026.03.24 MACRONIX INTERNATIONAL CO LTD
  • US12588574B2 patent drawing
  • US12588574B2 patent drawing
  • US12588574B2 patent drawing

AI summary

A compensation method for wafer bonding includes bonding a first wafer and a second wafer, the first wafer including a first conductive pad and a second conductive pad. A first overlay check is performed. A result of the first overlay check is determined whether the result is within a first predetermined specification. If the result of the first overlay check is determined as beyond the first predetermined specification, performing a first compensation method to form a compensated first wafer and a compensated second wafer, wherein a position of a first conductive pad of the compensated first wafer is different from a position of the first conductive pad of the first wafer, and a position of a second conductive pad of the compensated first wafer is different from a position of the second conductive pad of the first wafer.