Wafer Conductive Bump Density Layout for Uniform Electroplating
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Solution Overview
Problem
Conventional wafers face issues with resist layer remnants due to taller conductive bumps formed in ineffective areas during electroplating, hindering effective removal.
Innovation Solution
Differentially distribute conductive bumps in effective and ineffective areas to control current density, ensuring uniformity and adjust heights to match those in effective areas, facilitating easier resist layer removal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conductive bumps are formed with the same density in both effective and ineffective areas, then the manufacturing process is simple, but the current density becomes non-uniform causing taller bumps in ineffective areas that hinder resist layer removal
Solution Approach 1:
The patent applies local quality by varying the conductive bump density according to location: higher density in effective areas and lower density in ineffective areas. This localized differentiation ensures uniform current density distribution across the entire wafer surface during electroplating, preventing excessive bump height growth in ineffective areas and enabling complete resist layer removal.
Solution Approach 2:
The patent changes the density parameter of conductive bumps based on spatial location. By adjusting the bump density parameter from uniform to non-uniform distribution (higher in effective areas, lower in ineffective areas), the current density during electroplating is controlled to achieve uniform bump heights across different regions, solving the resist removal problem.
2Stability of the object's composition
If conductive bumps in ineffective areas are formed at the same height as effective areas, then the structure is uniform, but the resist layer cannot be effectively removed due to taller bumps blocking access
Solution Approach 1:
The patent uses local quality by creating different bump densities in different areas. The lower bump density in ineffective areas, combined with extended electroplating time, achieves the dual goal of uniform bump heights and complete resist removal, eliminating the harmful effect of resist remnants.
Solution Approach 2:
The patent applies preliminary action by extending the electroplating time before dicing. This additional plating time allows the conductive bumps in ineffective areas to grow to the required height to expose the resist layer fully, enabling complete resist removal before the subsequent dicing step.
3Manufacturing precision
If electroplating time is extended to increase bump heights, then bump uniformity improves, but manufacturing time and cost increase
Solution Approach 1:
The patent applies local quality by differentiating bump densities spatially. This allows the electroplating process to be optimized: the extended plating time is only partially needed because the lower density in ineffective areas naturally limits current consumption, reducing the overall time penalty while achieving uniform bump heights.
Solution Approach 2:
The patent changes the density parameter to optimize the electroplating process. By having higher density in effective areas and lower density in ineffective areas, the total current consumption is better managed, allowing extended plating time to achieve uniform heights without proportionally increasing manufacturing time and cost.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Reduces resist layer remnants by controlling current density and adjusting bump heights, enhancing manufacturing efficiency and yield.
Implementation Method 1
forming conductive bumps by electroplating
Data Source
AI summary
A wafer includes a substrate and conductive bumps on a surface of the substrate. In a plan view from a direction perpendicular to the surface of the substrate, the area density of the conductive bumps is higher in a first area than in a second area around the first area in the surface of the substrate. The first area has effective chip areas arranged therein.