Wafer Level Cantilever Pillar Structure for Board Reliability
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Solution Overview
Problem
Wafer-level QFN packages face reliability issues due to wafer warpage from thermal expansion mismatch and reduced board level reliability caused by pad size and solder connection voids, leading to unbalanced strain distribution in high-power electronics.
Innovation Solution
The implementation of a cantilever pillar design and segmented solder connection in wafer-level packaging, which includes forming pillars and dielectric layers on a semiconductor wafer, followed by the deposition of solder balls on these pillars to enhance solder joint strength and reduce connection stress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional flat no-lead packaging with standard pad size is used, then manufacturing is simpler, but board level reliability decreases due to solder connection voids and unbalanced strain distribution
Solution Approach 1:
The patent divides the solder connection structure into multiple segments by creating cantilever pillars with segmented solder connections. This segmentation allows for more uniform strain distribution across the solder joints, preventing concentration of stress at single points and thereby improving board level reliability without requiring a complete redesign of the packaging system
Solution Approach 2:
The patent transitions from a traditional two-dimensional pad structure to a three-dimensional cantilever pillar structure. By adding vertical dimensionality with pillars extending upward from the substrate, the design increases the solderable surface area and creates multiple attachment points, which improves reliability by distributing mechanical and thermal stresses across multiple dimensions rather than a single flat plane
2Strength
If pad size is increased to improve solder joint strength, then connection reliability improves, but footprint increases
Solution Approach 1:
The patent resolves this contradiction by moving from a planar expansion approach to a vertical expansion approach. Instead of increasing the horizontal footprint of pads, the design erects cantilever pillars that extend vertically, providing additional solderable surface area and joint strength while maintaining a compact horizontal footprint suitable for high-density applications
3Reliability
If thermal expansion mismatch is not addressed, then manufacturing is simpler, but wafer warpage occurs reducing reliability
Solution Approach 1:
The patent addresses thermal expansion mismatch by modifying the structural parameters of the packaging system. The cantilever pillars are designed with specific geometric parameters and material selections that accommodate differential thermal expansion between the wafer, substrate, and solder materials, allowing the structure to flex and absorb thermal stresses without warping while maintaining manufacturing feasibility
Data Source
AI summary
A wafer level package, electronic device including the wafer level package, and fabrication methods are described that include forming a cantilever pillar design as a portion of the wafer level package and/or a segmented solder connection for preventing and reducing connection stress and increasing board level reliability. In implementations, the wafer level device that employs example techniques in accordance with the present disclosure includes at least a section of a processed semiconductor wafer including at least one integrated circuit die, a first dielectric layer disposed on the processed semiconductor wafer, a first pillar, a second pillar formed on the first pillar, a second dielectric layer formed on the first dielectric layer and surrounding a portion of the first pillar and the second pillar, and at least one solder ball disposed on the second pillar.