Wafer CD Uniformity Control via Trim Time and Temperature
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Solution Overview
Problem
Existing methods for controlling critical dimension (CD) uniformity in semiconductor wafers during plasma etching struggle to achieve optimal results on a wafer-by-wafer basis, as they require multiple optimization steps and do not effectively compensate for non-uniformities resulting from process parameters, leading to variability in CD and CD uniformity.
Innovation Solution
A plasma processing system with independently controllable temperature control zones and a controller that adjusts temperature profiles based on data from previously processed wafers to calculate and apply a target trim time and temperature profile for each wafer, ensuring consistent CD uniformity across batches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple optimization steps are used to control CD target and CD uniformity, then the CD target can be achieved, but the process complexity increases and wafer-by-wafer adaptation becomes infeasible
Solution Approach 1:
The patent changes the temperature parameter dynamically based on wafer-specific characteristics. By adjusting the electrostatic chuck temperature according to measured CD uniformity data from previous wafers, the system adapts the etch process to compensate for variations in incoming wafers, achieving wafer-by-wafer optimization without requiring multiple iterative optimization steps
Solution Approach 2:
The patent implements a feedback mechanism where CD uniformity measurements from previously processed wafers are used to determine temperature adjustments for subsequent wafers. The controller receives measurement data, calculates appropriate temperature modifications, and applies these adjustments in real-time, creating a closed-loop control system that continuously optimizes CD uniformity
2Manufacturing precision
If iterative process is used to achieve desired post CD and CD uniformity target, then optimal results can be achieved, but the processing time increases and real-time adaptation is not feasible
Solution Approach 1:
The patent performs preliminary measurements on incoming wafers to determine their CD uniformity characteristics before processing. Based on these preliminary measurements and data from previously processed wafers, the controller pre-calculates the optimal temperature adjustment needed, eliminating the need for time-consuming iterative optimization during the actual etch process
Solution Approach 2:
The system pre-determines temperature parameter changes based on wafer characteristics measured before processing. By calculating the required temperature adjustment in advance using feedback from previous wafers, the system achieves optimal CD uniformity in a single pass without requiring multiple iterative cycles, thus reducing processing time
3Device complexity
If a single temperature control is used for the entire wafer, then the control system is simple, but it cannot compensate for spatial variations in CD uniformity across the wafer surface
Solution Approach 1:
The patent implements local quality control by dividing the wafer surface into multiple spatial zones, each with independent temperature control. The controller adjusts the temperature of specific zones based on the measured CD uniformity characteristics of corresponding regions on the wafer, allowing localized compensation for spatial variations without requiring complex multi-zone control systems
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for precise control of CD uniformity by adjusting temperature and trim time for each wafer, optimizing the etching process to achieve desired post-trim CD and CD uniformity targets, even when initial wafer dimensions and uniformity vary, thereby improving yield and consistency.
Implementation Method 1
the electrostatic chuck (ESC) temperature which controls the wafer surface reaction temperature
Implementation Method 2
processing the current wafer for a duration of the target trim time where the temperature of each device die location is adjusted
Data Source
AI summary
Exemplary embodiments are directed to controlling CD uniformity of a wafer by controlling trim time on temperature in a plasma processing system. The plasma processing system has a wafer support assembly including a plurality of independently controllable temperature control zones across a chuck and a controller that controls each temperature control zone. The controller receives process control and temperature data associated with at least one wafer previously processed in a plasma chamber of the plasma processing system. The controller also receives critical device parameters of a current wafer to be processed in the plasma chamber. The controller calculates a target trim time and a target temperature profile of the current wafer based on the process control and temperature data of the at least one previously processed wafers and the critical device parameters of the current wafer. The current wafer as subjected to a trimming operation for a duration of the target trim time while controlling temperatures in the temperature control zones to thereby control temperature of each device die location based on the target temperature profile.