Semiconductor Wafer Crack Guard Ring Design
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Solution Overview
Problem
Existing semiconductor wafer dicing techniques often result in cracks propagating from scribe areas into semiconductor chips, leading to chip breakage, and existing metal rings used to suppress crack propagation are not effective enough.
Innovation Solution
A semiconductor wafer design featuring a crack guard ring structure with multiple metal layers and a crack guard insulating film, where the upper metal layer is flush or recessed relative to the lower metal layer, and a crack guard window is formed to terminate cracks effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metal layers are stacked with the upper metal layer extending beyond the lower metal layer, then crack suppression coverage is improved, but manufacturing precision and structural stability deteriorate
Solution Approach 1:
Each metal layer is designed with different local qualities and positions. The first metal layer is at the lowest position, the second metal layer is at an intermediate position, and the third metal layer is at the highest position. This local differentiation creates a staggered configuration that provides comprehensive crack suppression coverage while maintaining manufacturability, as each layer serves a specific functional zone.
Solution Approach 2:
The metal layers are arranged in the vertical dimension (thickness direction) rather than extending horizontally beyond each other. This dimensional arrangement provides comprehensive coverage by distributing the metal layers at different heights, achieving crack suppression effectiveness without the alignment precision problems that would arise from horizontal extension.
Data Source
AI summary
A semiconductor wafer includes: a first semiconductor chip area formed with a semiconductor element; a second semiconductor chip area formed with a semiconductor element; and a scribe area sandwiched between the first and second semiconductor chip areas; wherein: the first semiconductor chip area includes a first metal ring surrounding the semiconductor element formed in the first semiconductor chip area; and the metal ring is constituted of a plurality of metal layers including a lower metal layer and an upper metal layer superposed upon the lower metal layer, and the upper metal layer is superposed upon the lower metal layer in such a manner that an outer side wall of the upper metal layer is flush with the outer side wall of the lower metal layer or is at an inner position of the first semiconductor chip area relative to the outer side wall of the lower metal layer.