Wafer Dicing via Scribe Line Etch for Low-k Dielectric Integrity
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Solution Overview
Problem
The separation of semiconductor chips with low-k dielectric materials using diamond saws leads to mechanical stress, cracking, and peeling due to the brittle nature of these materials, compromising the reliability and integrity of the devices, especially in backside-illuminated image sensors where bonding interfaces add to the weakness.
Innovation Solution
A dual-step die separation process involving etching to remove low-k dielectric materials at scribe lines instead of using a die saw, reducing mechanical stress and peeling, followed by sawing to separate the carrier wafer, thereby minimizing stress fractures and enhancing reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If diamond saw is used to separate dies, then die separation is achieved, but mechanical stress causes cracking and peeling of low-k dielectric materials
Solution Approach 1:
The die separation process is divided into two distinct stages: first, an etch process removes material from the device wafer down to the carrier wafer, creating a weakened scribe line; second, a saw process completes the separation by cutting through the carrier wafer. This segmentation allows each process to be optimized independently, with the etch process protecting the low-k dielectric from mechanical stress while the saw process provides clean final separation.
Solution Approach 2:
The etched scribe line acts as an intermediary weakened zone that facilitates separation. By removing material to create this intermediate structure, the subsequent sawing process encounters reduced resistance and generates less mechanical stress on the low-k dielectric regions, thereby preventing cracking and peeling while maintaining die integrity.
2Reliability
If low-k dielectric materials are used to reduce parasitic capacitance, then cross coupling is reduced, but the materials become brittle and prone to peeling and cracking
Solution Approach 1:
The etch process selectively removes material from the scribe line regions, extracting the vulnerable low-k dielectric material from areas where mechanical stress will be applied during separation. This extraction eliminates the weak link in the mechanical chain while preserving the low-k dielectric material in the functional die regions where its electrical properties are critical for reducing parasitic capacitance and cross coupling.
3Ease of manufacture
If device wafer is bonded to carrier wafer for BSI image sensor fabrication, then further processing is enabled, but bonding interface becomes a weak point for peeling and cracking
Solution Approach 1:
The etch process is performed preliminarily to weaken the scribe line through the device wafer and into the carrier wafer before the final sawing separation. This preliminary action creates a controlled weakened zone that guides the subsequent saw cut, reducing the risk of unpredictable cracking at the bonding interface during the separation process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method reduces the occurrence of peeling and cracking, increases the number of good dies per wafer, and compensates for additional costs by improving the reliability and integrity of the separated chips, particularly for backside-illuminated image sensors.
Implementation Method 1
A dual-step die separation process involving etching to remove low-k dielectric materials at scribe lines
Data Source
AI summary
Embodiments of a method for separating dies from a wafer having first and second sides. The process embodiment includes masking the first side of the wafer, the mask including openings therein to expose parts of the first side substantially aligned with scribe lines of the wafer. The process embodiment also includes etching from the exposed parts of the first side of the wafer until an intermediate position between the first and second sides and sawing the remainder of the wafer, starting from the intermediate position until reaching the second surface.