Wafer-Level Full-Color Display Interconnect Layout Over LED Step Heights
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Solution Overview
Problem
The manufacturing of full-color LED display devices is hindered by the difficulty in forming conductive lines that need to climb over height differences of several microns between P-type and N-type semiconductor epitaxial layers, leading to broken circuits and reduced yield.
Innovation Solution
A method involving the formation of insulating layers to fill trenches between LED structures, creating leveling layers on which circuit layers are formed, thereby leveling the height differences and preventing conductive line breaks, allowing for flexible circuit design and increased yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conductive lines are formed to connect P-type and N-type semiconductor epitaxial layers, then electrical connection is achieved, but the conductive lines are prone to breaking due to height differences of several microns
Solution Approach 1:
The patent divides the LED array into modular units with standardized pitches, and segments the circuit connections into discrete conductive lines that follow the module boundaries. This segmentation allows conductive lines to connect adjacent modules at similar elevation levels, avoiding the need to climb over height differences of several microns between P-type and N-type layers, thereby reducing breakage risk while maintaining electrical connectivity.
Solution Approach 2:
The patent transitions from planar circuit routing to three-dimensional stacking, where conductive lines are formed on the same horizontal plane (z-dimension) rather than attempting to connect layers at different heights. By routing all conductive connections through the wafer thickness dimension rather than laterally across height differences, the design eliminates the climbing problem while achieving electrical connection between P-type and N-type structures.
2Productivity
If traditional LED manufacturing processes are used, then LED structures are formed, but transfer steps are required which reduce production efficiency and increase costs
Solution Approach 1:
The patent merges the LED structure formation and circuit pattern formation into a single integrated wafer fabrication process. Both the LED active regions and the circuit interconnects are defined and formed simultaneously on the same wafer substrate before any transfer or separation steps, eliminating the need for separate transfer processes and thereby improving productivity while reducing overall process complexity.
Solution Approach 2:
The patent performs preliminary circuit pattern formation and conductive line creation on the wafer substrate before the LED modules are separated or transferred. By establishing the complete circuit architecture in advance on the intact wafer, the design eliminates subsequent transfer steps that would otherwise be required to move circuits to final substrates, thereby streamlining manufacturing and improving production efficiency.
3Manufacturing precision
If conductive lines must climb over height differences between epitaxial layers, then vertical electrical connection is achieved, but the manufacturing precision required increases significantly
Solution Approach 1:
The patent segments the LED array into modular units with standardized pitches, and segments the circuit connections into discrete conductive lines that follow the module boundaries. This segmentation allows conductive lines to connect adjacent modules at similar elevation levels, avoiding the need to climb over height differences of several microns between P-type and N-type layers, thereby reducing breakage risk while maintaining electrical connectivity.
4Measurement precision
If LED structures are arranged densely to increase display resolution, then pixel density improves, but the height difference between P-type and N-type layers becomes more problematic
Solution Approach 1:
The patent transitions from planar circuit routing to three-dimensional stacking, where conductive lines are formed on the same horizontal plane (z-dimension) rather than attempting to connect layers at different heights. By routing all conductive connections through the wafer thickness dimension rather than laterally across height differences, the design eliminates the climbing problem while achieving electrical connection between P-type and N-type structures.
Data Source
AI summary
A wafer-level full-color display device and a method for manufacturing the same are provided. In the method, a plurality of LED structures arranged into an array and a peripheral electrode layer surrounding the LED structures are formed on a front side of a wafer substrate. Next, one or more insulating layers are formed to flatten the stepped difference of each of the LED structures and fill up the height difference between the LED structures and the wafer substrate. Afterwards, conductive lines are formed on the one or more insulating layers to provide a reliable electrical connection between the LED structures and the peripheral electrode layer.