Wafer Geometry Gapi Metric for Early Distortion Prediction
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Solution Overview
Problem
Conventional metrology tools are insufficient for predicting wafer distortion before the fabrication process, leading to overlay errors and reduced back-end yield due to elastic deformation during layer formation on semiconductor wafers.
Innovation Solution
The implementation of a Gapi wafer geometry metric generated from front-end processed semiconductor wafer measurement data, allowing for early identification and adjustment of front-end process tools to improve wafer flatness and reduce distortion, thereby enhancing back-end yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional metrology tools are used to measure wafer geometry, then measurement capability is limited to polished surfaces, but wafer distortion prediction before fabrication is insufficient
Solution Approach 1:
The patent applies preliminary action by measuring wafer geometry at the front-end processing stage before fabrication begins. The system captures thickness and surface profile data from wafers immediately after front-end processing (grinding, lapping, etching) but before polishing and lithography. This early measurement enables prediction of elastic deformation and overlay errors that will occur during subsequent fabrication steps, allowing corrective actions to be taken beforehand.
Solution Approach 2:
The patent introduces an intermediary metric called Gapi (Geometry Aperture Index) that bridges the gap between front-end processed wafer geometry and back-end overlay performance. The Gapi metric is calculated from thickness and surface profile measurements taken at the front-end stage, and serves as a predictor for wafer distortion during fabrication. This intermediary measurement enables correlation between early-stage geometry and late-stage overlay errors without requiring direct measurement at both stages.
2Measurement precision
If high accuracy inspection tools are used to measure wafer distortion, then measurement precision is improved, but device complexity and processing time increase
Solution Approach 1:
The patent extracts the essential geometry measurement capability from complex high-accuracy inspection tools and applies it at the front-end processing stage. Instead of using sophisticated Patterned Wafer Geometry metrology systems that require polished surfaces and complex optics, the system uses simpler thickness and surface profile measurements from front-end processed wafers. This extraction enables distortion prediction using less complex equipment while maintaining predictive accuracy through the Gapi metric.
3Reliability
If wafer measurements are taken after fabrication begins, then distortion can be detected, but overlay errors have already occurred reducing back-end yield
Solution Approach 1:
The patent implements preliminary action by performing wafer geometry measurement and Gapi calculation at the front-end processing stage, before any lithography or pattern formation occurs. This timing allows identification of wafers that will develop overlay errors during fabrication, enabling sorting and removal of problematic wafers before they enter the fabrication process. Consequently, back-end yield is improved by preventing overlay errors rather than detecting them after damage has occurred.
Data Source
AI summary
A method for processing semiconductor wafers includes obtaining measurement data from a surface of a semiconductor wafer processed by a front-end process tool. The method includes determining a center plane of the wafer based on the measurement data, generating raw shape profiles, and generating ideal shape profiles. The method further includes generating Gapi profiles based on the raw shape profiles and the ideal shape profiles, and calculating a Gapi value of the semiconductor wafer based on the Gapi profiles. The generated Gapi profiles and/or the calculated Gapi value may be used to tune the front-end process tool and/or sort the semiconductor wafer for polishing. Systems include at least a front-end process tool, a flatness measurement tool, and a computing device.


