Semiconductor Wafer Flatness Control via Hard Polishing Pad
Solution Overview
Problem
Existing semiconductor wafer manufacturing processes struggle to meet multiple flatness indexes such as SFQR, ESFQR, ZDD, ROA, GBIR, and SBIR simultaneously due to issues with outer peripheral sag and curvature changes, especially when using soft polishing pads, which limits productivity and yield.
Innovation Solution
A semiconductor wafer with a center convex shape and controlled outer peripheral sag, where the displacement between the center and outer peripheral sag start position is 100 nm or less, and the sag start position is 20 mm or more from the outer peripheral end, combined with double-sided polishing and chemical-mechanical polishing using high-hardness polishing pads, to minimize deviations from reference surfaces and suppress curvature changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If soft polishing pads are used to reduce scratches on wafer surface, then scratch reduction is achieved, but outer peripheral sag increases due to polishing pad deformation
Solution Approach 1:
The patent changes the hardness parameter of the polishing pad from soft to hard, which fundamentally alters the polishing mechanism. Hard polishing pads maintain their shape during polishing, preventing the deformation that causes outer peripheral sag, while still achieving scratch-free surfaces through controlled material removal
Solution Approach 2:
Instead of using soft polishing pads to reduce scratches (conventional approach), the patent inverts the approach by using hard polishing pads. This inversion resolves the contradiction by eliminating the root cause of sag (pad deformation) while maintaining scratch reduction through precise polishing control
2Measurement precision
If outer peripheral excluded region is reduced to improve ESFQR measurement accuracy, then measurement precision improves, but outer peripheral sag has greater influence on the measurement
Solution Approach 1:
The patent applies preliminary action by using hard polishing pads from the beginning of the polishing process to prevent outer peripheral sag formation. This preliminary prevention ensures that when ESFQR measurement is performed with minimal excluded region, the outer peripheral area is already flat and free from sag-induced measurement errors
Solution Approach 2:
Changing the polishing pad hardness parameter fundamentally alters the surface profile development during polishing. Hard pads produce a more uniform thickness distribution across the wafer, including the outer peripheral region, thereby improving both measurement precision and manufacturing precision simultaneously
3Measurement precision
If multiple flatness indexes are measured with different reference surfaces and edge exclusions, then comprehensive flatness evaluation is achieved, but it becomes difficult to meet all indexes simultaneously
Solution Approach 1:
The patent creates a universal polishing solution using hard polishing pads that simultaneously satisfies multiple flatness evaluation criteria. The hard pad produces a consistent, controlled surface profile that performs well across different measurement standards (GBIR, SFQR, SBIR, ESFQR, ROA, ZDD) without requiring separate optimization for each index
Solution Approach 2:
By changing the polishing pad hardness parameter, the patent achieves a surface profile that is robust across multiple measurement conditions. The hard pad creates a predictable thickness distribution that meets various flatness specifications simultaneously, resolving the difficulty of complying with multiple indexes
4Productivity
If conventional polishing processes are used to maintain productivity, then production speed is maintained, but outer peripheral sag occurs due to polishing pad deformation
Solution Approach 1:
The patent changes the polishing pad hardness parameter to hard, which eliminates pad deformation during polishing. This parameter change allows conventional high-speed polishing processes to continue without causing outer peripheral sag, thereby maintaining productivity while improving shape accuracy
Solution Approach 2:
The patent substitutes the soft polishing pad mechanical system with a hard polishing pad system. This substitution changes the mechanical interaction between pad and wafer, preventing pad deformation and the resulting sag while allowing conventional polishing speeds to be maintained
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for simultaneous meeting of multiple flatness indexes across different edge exclusions and reference surfaces, improving productivity and yield by maintaining consistent processing conditions and reducing sag-related issues.
Implementation Method 1
A removal stock of the polished semiconductor wafer outer peripheral portion increases due to contact with a polishing pad
Implementation Method 2
one side of the semiconductor wafer is then subjected to chemical-mechanical polishing
Data Source
AI summary
A semiconductor wafer having sag formed at an outer periphery at the time of polishing, wherein a displacement of the semiconductor wafer in a thickness direction is 100 nm or less between a center and a outer peripheral sag start position of the semiconductor wafer, and the center of the semiconductor wafer has a convex shape, an amount of outer peripheral sag of the semiconductor wafer is 100 nm or less, and the outer peripheral sag start position is away from an outer peripheral portion of the semiconductor wafer toward the center or 20 mm or more away from an outer peripheral end of the semiconductor wafer toward the center, the outer peripheral portion being a measurement target of ESFQR.