Wafer-Level LED Chip Integration With CMOS and Mold Compound
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Solution Overview
Problem
Existing methods for manufacturing semiconductor chips face challenges in integrating light-emitting epitaxial semiconductor layer stacks with logical chips efficiently, particularly in maintaining mechanical stability and simplifying the manufacturing process while ensuring effective control of electromagnetic radiation generation.
Innovation Solution
A method involving the integration of epitaxial semiconductor layer stacks with logical chips on a wafer level, using a mold compound for stabilization, and applying logical chips over an epitaxial semiconductor layer sequence, followed by singulation into individual chips, with additional features like protection and contrast enhancement structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple logical chips are integrated with epitaxial semiconductor layer stacks on wafer level, then manufacturing efficiency and productivity are improved, but device complexity and process difficulty increase
Solution Approach 1:
The method segments the manufacturing process into distinct stages: providing epitaxial semiconductor layer stacks on a wafer, applying multiple logical chips to the wafer surface, embedding in mold compound, and final singulation. This segmentation allows each stage to be optimized independently while maintaining overall productivity.
Solution Approach 2:
The patent transitions from traditional individual chip processing to wafer-level parallel processing, adding a spatial dimension to manufacturing. Multiple logical chips are applied simultaneously to different locations on the wafer surface, enabling parallel production and significantly improving productivity.
2Productivity
If logical chips are applied on epitaxial semiconductor layer sequence before singulation, then integration efficiency is improved, but mechanical stability deteriorates
Solution Approach 1:
The mold compound acts as an intermediary material that embeds both the logical chips and epitaxial semiconductor layer stacks during the wafer-level integration process. This intermediary provides mechanical support and stability to the combined structure, allowing efficient integration while maintaining structural integrity before final singulation.
3Loss of time
If wafer-level integration method is used, then manufacturing time is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The method performs preliminary actions at the wafer level before singulation, including applying multiple logical chips to the epitaxial semiconductor layer sequence and embedding in mold compound. By completing these operations while the wafer maintains its structural integrity, the process reduces total manufacturing time while the mold compound provides the necessary precision support during chip-level operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances mechanical stability and simplifies the manufacturing process, allowing efficient control of electromagnetic radiation generation and integration of logical chips, while maintaining the integrity of the semiconductor chips.
Implementation Method 1
an active region configured for generating electromagnetic radiation, particularly visible light, during operation
Data Source
AI summary
In an embodiment a method for manufacturing a plurality of semiconductor chips includes providing an epitaxial semiconductor layer sequence having a plurality of epitaxial semiconductor layer stacks, the epitaxial semiconductor layer stacks having active regions configured for generating electromagnetic radiation, applying a plurality of logical chips on or over the epitaxial semiconductor layer sequence, the logical chips including at least one integrated circuit configured for controlling the active regions, wherein the logical chips are at least partially provided separately from each other, and wherein the logical chips are CMOS chips, the CMOS chips including at least one p-channel MOSFET and at least one n-channel MOSFET being part of the at least one integrated circuit, and embedding the plurality of logical chips in a mold compound.