System-on-Wafer 3D Stacking for Dense Heterogeneous Integration
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Solution Overview
Problem
Existing semiconductor technologies face limitations in integrating heterogeneous functional structures on wafers, leading to inefficient integration and low function density in system on wafer (SoW) applications, which are not adequately addressed by current chip-level and wafer-level integration methods.
Innovation Solution
The method involves wafer-level design and integration of multi-wafer arrays with stacked structures, utilizing similar IC processes to bond wafers with functional/sensor devices, electrical interconnect layers, back-end dies, and heat dissipation modules, enabling functional reconfiguration and intelligent collaboration among devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If chip-level integration technology of system on chip (SoC) is used with interposer for heterogeneous integration, then functional integration is achieved, but integration density and system power are reduced
Solution Approach 1:
The patent transitions from chip-level 2D integration to wafer-level 3D stacked integration. Multiple wafers are bonded vertically to form a stacked structure, enabling heterogeneous integration of computation dies, storage dies, and heat dissipation modules in the third dimension, thereby dramatically increasing integration density while maintaining functional versatility
Solution Approach 2:
The patent merges multiple separate chips/dies onto a single wafer substrate through wafer-level bonding. Computation dies, storage dies, and heat dissipation modules are combined into one integrated wafer-scale system, achieving both functional integration and high integration density simultaneously
2Adaptability or versatility
If discrete integration of chips relying on interposer in SoC is used, then heterogeneous integration is achieved, but system power consumption increases
Solution Approach 1:
The patent employs 3D vertical stacking with through-wafer vias (TSV) to create short interconnect paths between computation dies, storage dies, and heat dissipation modules. This vertical integration dramatically reduces signal transmission distance compared to discrete chip interconnections, thereby lowering power consumption while maintaining heterogeneous integration capabilities
3Device complexity
If simple stacked integration of same dies is used, then integration is achieved, but function density is limited by ceiling effect
Solution Approach 1:
The patent assigns different functional qualities to different regions and layers of the wafer stack. Computation dies are placed in specific layers, storage dies in others, and heat dissipation modules in dedicated regions. This localized functional differentiation maximizes function density by ensuring each region contributes its specialized capability to the overall system
Solution Approach 2:
The patent creates a composite wafer structure integrating multiple material types and functional components: semiconductor computation dies, storage dies, heat dissipation materials, and interconnect structures. This composite approach enables diverse functions to coexist in a single integrated system, breaking the ceiling effect of homogeneous stacking
4Quantity of substance
If wafer-level integration technology of system on wafer (SoW) is used with multi-wafer bonding, then integration density is improved, but manufacturing complexity increases
Solution Approach 1:
The patent performs preliminary processing and preparation of multiple wafers before bonding. Dies are pre-sorted, pre-positioned, and pre-aligned on separate wafers according to the final stacked configuration. This preliminary action simplifies the actual bonding process and reduces manufacturing complexity despite the high integration density achieved
Solution Approach 2:
The patent divides the complex wafer-level integration process into manageable segments: separate preparation of computation dies, storage dies, and heat dissipation modules on individual wafers; followed by staged bonding operations. This segmentation of the manufacturing process makes the complex integration task more controllable and manufacturable
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances integration and function density of SoW by allowing functional reconfiguration and intelligentization through electrical interconnections and heat dissipation, improving performance and efficiency.
Implementation Method 1
heat dissipation modules, enabling functional reconfiguration and intelligent collaboration among devices
Implementation Method 2
electrical interconnect layers, back-end dies, and heat dissipation modules, enabling functional reconfiguration
Data Source
AI summary
The present disclosure discloses wafer-level design, manufacturing, and integration methods of system on wafer (SoW). Through similar integrated circuit (IC) processes, the heterogeneous functional structures of devices (dies) are prepared on a wafer (layer); then the multi-wafers with different functional structures are bonded to form high density devices (dies) with complete functions; and the wafer-level functions are reconfigured to form the intelligent microsystem (SoW). Based on the existing semiconductor manufacturing and packaging technology, the functional/sensor devices (dies), electrical interconnect layers, back-end dies, and heat dissipation modules are integrated to form the SoW, which can realize the functional reconfiguration and intelligent collaborative control under the collaboration of multifunctional dies within the SoW, and dramatically improve the integration and function density of the SoW, to realize intelligentization.