Wafer-Level Bus Flow Control for Multi-Die Latency
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Solution Overview
Problem
The challenge is to design a high-performance communication bus protocol for semiconductor dies in a wafer-level package that addresses the low yield and high cost of large-sized dies and the latency issues in communication between multiple small-sized dies, while minimizing overhead and latency.
Innovation Solution
The solution involves implementing a flow control mechanism using a bus master and bus slave architecture with a communication interface, where the bus master is controlled by a flow control mechanism to manage transaction flow, and the bus slave can trigger back-pressure or credit-based mechanisms to manage transaction flow, ensuring high bandwidth and low latency communication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If a large-sized die is used to achieve a chip function, then the die area is sufficient for complex functions, but the fabrication yield is low and cost is high
Solution Approach 1:
The patent divides a large die into multiple smaller dies, each capable of performing specific functions independently. These smaller dies are then assembled in a wafer-level package to achieve the overall chip function. This segmentation increases fabrication yield since smaller dies have lower defect rates while maintaining the functional capability through parallel operation of multiple dies.
2Productivity
If one large die is split into multiple small dies, then the fabrication yield improves, but a large number of signals are introduced for communication between dies
Solution Approach 1:
The patent employs a universal bus interface that can handle multiple types of transactions (read, write, read-modify-write, etc.) through a standardized protocol. This multi-functional interface reduces the need for dedicated signal lines for each type of communication, as a single bus can perform various operations by interpreting control signals and transaction types.
Solution Approach 2:
The patent changes the communication paradigm from dedicated signal lines to a parameter-based bus protocol where information is encoded in transaction parameters (address, data, control signals). This allows the same physical bus to carry different types of information by changing the parameters of the transactions, thereby reducing the number of physical signals required.
3Reliability
If a real-time handshaking mechanism is employed between bus master and bus slave, then communication reliability is improved, but the communication bus performance is degraded due to long latency
Solution Approach 1:
The patent implements a flow control mechanism that performs preliminary actions by setting up transaction queues and pre-negotiating bandwidth allocation before actual data transfer. The bus master can queue multiple transactions in advance, and the flow control mechanism pre-establishes the communication parameters, allowing transactions to proceed with minimal handshaking overhead and reduced latency.
Solution Approach 2:
The patent enables continuous data transfer through burst transactions and flow-controlled bus access. Once the bus master gains access to the bus, it can continue transmitting multiple transactions in a burst without repeated handshaking, maintaining continuous useful action. The flow control mechanism ensures that the bus slave is ready to receive or send data, eliminating idle time and reducing overall latency.
Data Source
AI summary
A semiconductor die assembled in a wafer-level package includes a communication interface and a bus master. The bus master is coupled to a communication bus through the communication interface. The bus master communicates with a bus slave of another semiconductor die assembled in the wafer-level package via the communication bus, and is controlled by a flow control mechanism that manages a transaction flow initiated by the bus master over the communication bus.