Wafer-Level Packaging Method With Cavity Interconnection

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Solution Overview

Problem

Current wafer-level packaging methods are complex and require additional connection structures, which complicates the process and necessitates the removal of injection molding layers, increasing labor and equipment requirements.

Innovation Solution

A simplified wafer-level packaging method where a first wafer with integrated first chips and a second wafer with integrated second chips are bonded, forming a cavity between electrodes, with a chip interconnection structure electrically connecting the electrodes, eliminating the need for additional connection structures and simplifying the process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional WLSiP packaging method is used with additional connection structures, then electrical connections can be established, but the packaging process becomes complex and requires removal of injection molding layers

Engineering Contradiction:

Improveelectrical connection reliabilityVSAvoidpackaging process complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the electrical connection function directly into the bonding interface between first and second chips. The bonding layer serves dual purposes: mechanical bonding and electrical connection, eliminating the need for separate connection structures and injection molding layer removal steps.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The bonding layer is designed to perform multiple functions simultaneously: it provides mechanical bonding between chips and establishes electrical connections through conductive particles. This multi-functionality simplifies the overall packaging process by eliminating redundant steps.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Reliability

If additional connection structures are used in WLSiP packaging, then electrical connections are established, but labor amount and equipment requirements increase

Engineering Contradiction:

Improveelectrical connection reliabilityVSAvoidmanufacturing simplicity

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The bonding and electrical connection processes are merged into a single step. The bonding layer with conductive particles establishes both mechanical and electrical connections simultaneously, reducing labor and equipment requirements compared to separate processing steps.

Inventive Principle:

Principle #5Merging (Combining)

3Manufacturing precision

If injection molding layers are removed in conventional WLSiP, then packaging accuracy is improved, but the process requires additional labor and equipment

Engineering Contradiction:

Improvepackaging accuracyVSAvoidprocess steps

Core Design Contradiction:

Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent extracts and eliminates the injection molding layer from the packaging structure entirely. By using a bonding layer with conductive particles that serves both bonding and electrical connection functions, the injection molding layer and its removal steps become unnecessary.

Inventive Principle:

Principle #2Taking out (Extraction)

4Reliability

If conventional packaging integration process is used, then electrical connections can be established, but the package area is larger and manufacturing cost is higher

Engineering Contradiction:

Improveelectrical connection reliabilityVSAvoidpackage area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent merges multiple functions (bonding, electrical connection, and encapsulation) into integrated layers, eliminating the need for separate connection structures that would increase package area. This integration reduces both the physical footprint and manufacturing cost.

Inventive Principle:

Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method reduces manufacturing costs and labor, optimizes electronic performance, and simplifies the packaging process by directly connecting first and second electrodes within the cavity, enhancing reliability and efficiency.

Implementation Method 1

A bonding process to physically bond a chip to be integrated to a wafer

Methodology Applied

Scientific EffectBonding: Welding

Implementation Method 2

using an electroplating process to electrically connect semiconductors

Methodology Applied

Scientific EffectElectroplating: Electroplating

Implementation Method 3

using a through-silicon via (TSV) process to electrically connect a chip with external electric circuits

Methodology Applied

Scientific EffectConduction: Conduction (electrical)

Data Source

PatentUS10804177B2Wafer-level packaging method and package structure thereof

Publication Date: 2020.10.13 NINGBO SEMICON INT CORP

AI summary

A wafer-level packaging method and a package structure are provided. In the method, a first wafer is provided having first chips formed there-in. A surface of each first chip is integrated with a first electrode. A first dielectric layer is formed on the first wafer to expose each first electrode. Second chips are provided with a surface of each second chip integrated with a second electrode. A second dielectric layer is formed on the plurality of second chips to expose each second electrode. The second dielectric layer is positioned relative to the first dielectric layer. The second chips are bonded to the first wafer with each second chip aligned relative to one first chip to form a cavity there-between. A chip interconnection structure is formed in the cavity to electrically connect the first electrode with the second electrode. An encapsulation layer covers the second chips.