Wafer-Level Chip-on-Chip Package Vertical Stacking
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Solution Overview
Problem
Conventional semiconductor packages face challenges in minimizing mounting area and solder joint reliability due to horizontal chip arrangement and differences in thermal expansion coefficients between plastic substrates and semiconductor chips, leading to increased mounting height and non-wet defects.
Innovation Solution
The implementation of a silicon-wafer-level chip-on-chip package and package-on-package structure, where semiconductor chips are vertically stacked using a silicon wafer substrate, with a redistribution layer and solder balls for improved connectivity and thermal expansion matching, and a protection member to enhance solder joint reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If semiconductor chips are arranged horizontally in a conventional SIP, then the mounting area increases, but the chip integration is achieved
Solution Approach 1:
The patent transitions from horizontal chip arrangement to vertical stacking arrangement, utilizing the third dimension (height) to accommodate multiple chips. This dimensional change allows multiple semiconductor chips to be integrated without increasing the planar mounting area, as chips are stacked one above another rather than placed side by side.
Solution Approach 2:
The patent implements a nested structure where multiple semiconductor chips are stacked vertically within a single package substrate. Each chip is positioned above the previous one, creating a nested configuration that maximizes space utilization and reduces the overall mounting footprint while maintaining high chip density.
2Length of stationary object
If a plastic substrate is used to stack semiconductor chips, then the mounting height is reduced, but non-wet defects occur due to CTE mismatch
Solution Approach 1:
The patent changes the substrate material parameter from plastic to silicon wafer. This material substitution fundamentally alters the coefficient of thermal expansion to match that of the semiconductor chips, eliminating the CTE mismatch problem that causes non-wet defects during reflow soldering, while maintaining the reduced mounting height objective.
Solution Approach 2:
The patent achieves homogeneity in thermal expansion properties by using a silicon wafer substrate that has a CTE closely matching the semiconductor chips. This homogeneous thermal behavior across all components prevents differential expansion and contraction during temperature cycling, thereby preventing solder joint failures and non-wet defects.
3Strength
If solder balls are fully embedded in molding compound, then the package is protected, but solder joint reliability decreases
Solution Approach 1:
The patent applies local quality by selectively exposing certain solder balls at the top surface of the molding compound while keeping others embedded. This localized differentiation allows specific solder balls to serve as external connection points with direct access, improving solder joint reliability for inter-package connections, while other embedded solder balls continue to provide mechanical strength and protection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach minimizes the mounting area and height of semiconductor packages, reduces warping due to thermal expansion differences, and enhances solder joint reliability by using a silicon wafer substrate and epoxy mold compound to partially expose solder balls.
Implementation Method 1
differences in thermal expansion coefficients between plastic substrates and semiconductor chips
Implementation Method 2
packages are connected using solder balls having better attaching performance to improve solder joint reliability
Data Source
AI summary
A method of manufacturing a multi-chip package in which a plurality of semiconductor chips are mounted on a single package using a chip-on-chip technique reduces warping due to a difference in coefficients of thermal expansion (CTEs) between a printed circuit board (PCB) and a stacked semiconductor chip. A package on package is manufactured by vertically stacking packages to operate a memory semiconductor chip package and a logic semiconductor chip package in a single system. To improve a non-wet defect of solder balls used to connect packages and minimize the mounting height of the package on package, a protection member formed of an epoxy mold compound (EMC) is formed on the memory semiconductor chip package to only partially expose the solder balls, and the exposed portions of the solder balls are connected to vias formed in a rear surface of the logic semiconductor chip package using a solder ball attaching process.