Wafer-Level Chip Package Manufacturing with Trench Dicing
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Solution Overview
Problem
Conventional chip packaging methods are time-consuming and prone to alignment offset issues due to the complex and labor-intensive process of arranging and dicing semiconductor dies.
Innovation Solution
A method involving wafer dicing to form trenches, forming conductive bumps and a patterned photoresist layer, thinning the wafer, and creating an insulating layer to produce chip packages, which includes steps like forming an adhesive layer and a carrier board to address alignment and reduce processing time and costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If semiconductor dies are arranged one by one on a carrier board for packaging, then chip packages can be formed in batch, but the process becomes time-consuming and complicated with alignment offset issues
Solution Approach 1:
The patent applies preliminary action by forming conductive bumps on the wafer surface before dicing, and by pre-arranging the wafer structure with trenches and photoresist patterns. This allows the wafer to be diced into individual chip packages with pre-formed conductive connections, eliminating the need for time-consuming post-dicing bump formation and alignment operations. The preliminary structuring of the wafer enables batch processing while maintaining precision.
2Productivity
If semiconductor dies are arranged one by one on a carrier board, then batch packaging is achieved, but alignment offset issues occur
Solution Approach 1:
The patent merges the formation of conductive bumps, photoresist patterning, and wafer structuring into a single integrated process that occurs before dicing. By combining these operations while the wafer remains intact, the method ensures precise relative positioning of all components. The merged process eliminates sequential alignment steps that would otherwise introduce offset errors, achieving both batch production and high precision.
Solution Approach 2:
The patent utilizes the wafer's three-dimensional structure by forming trenches and filling them with photoresist and conductive material. This vertical dimensionality allows conductive bumps to be formed within the wafer body rather than on the surface, providing mechanical interlocking and precise alignment that prevents offset issues during subsequent handling and packaging operations.
3Ease of manufacture
If conventional dicing and packaging methods are used, then individual chip packaging is achieved, but the process is time-consuming and complicated
Solution Approach 1:
The patent performs preliminary structuring of the wafer by forming trenches, filling with photoresist, and creating conductive bumps before dicing. This preliminary action consolidates multiple manufacturing steps into one batch process, simplifying the overall manufacturing流程 and reducing total processing time while maintaining ease of manufacture through standardized wafer-level operations.
Data Source
AI summary
A method for manufacturing chip package is disclosed. The method includes providing a wafer having an upper surface and a lower surface opposite thereto, in which the wafer comprises a plurality of conductive pads disposed on the upper surface; dicing the upper surface of the wafer to form a plurality of trenches; forming a patterned photoresist layer on the upper surface and in the trenches; forming a plurality of conductive bumps disposed correspondingly on the conductive pads; thinning the wafer from the lower surface toward the upper surface, such that the patterned photoresist layer in the trenches is exposed from the lower surface; forming an insulating layer under the lower surface; and dicing the patterned photoresist layer and the insulating layer along each trench to form a plurality of chip packages.