Wafer-Level Chip Stacking via Gap-Filling and Carrier Bonding
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The packaging of integrated circuits involves lengthy process cycles, low throughput, and high costs due to the need for multiple pick-and-place processes to stack individual chips, which is inefficient and costly.
Innovation Solution
The approach involves bonding wafers instead of individual chips, using direct wafer bonding and hybrid bonding techniques to stack chips, reducing the need for individual chip placement and improving throughput by using wafers with pre-formed through-vias and gap-filling materials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If individual chips are picked and placed one by one to stack multiple levels, then precise positioning and electrical connectivity are achieved, but the process cycle time increases and throughput decreases
Solution Approach 1:
Multiple individual chip placement operations are merged into a single wafer-level bonding operation. The entire wafer containing multiple chips is bonded to the substrate in one step, eliminating the need for sequential pick-and-place operations for each chip. This merging of operations maintains positioning precision through wafer-level alignment while dramatically increasing throughput by processing multiple chips simultaneously.
Solution Approach 2:
Chips are pre-arranged and pre-positioned on the wafer before the bonding process. The wafer serves as a pre-assembled carrier that holds multiple chips in their final positions, eliminating the need for individual positioning during the packaging process. This preliminary arrangement of chips on the wafer enables high-speed bonding while maintaining precise spatial relationships between chips.
2Ease of manufacture
If multiple pick-and-place processes are used for each level of chips, then individual chip placement is achieved, but the process complexity and manufacturing cost increase
Solution Approach 1:
Multiple separate pick-and-place processes for different chip levels are merged into a single wafer bonding process. Instead of performing individual placement operations for each chip at each level, the entire wafer is bonded in one step, significantly reducing process complexity while maintaining the capability to achieve precise chip placement through wafer-level alignment and bonding techniques.
Solution Approach 2:
The wafer serves as an intermediary carrier that simplifies the manufacturing process. Rather than directly placing individual chips onto the substrate through complex pick-and-place operations, the wafer acts as a pre-assembled intermediate structure that can be bonded to the substrate in a single operation, reducing the number of process steps and overall complexity.
3Reliability
If gap-filling and planarization processes are performed after each level of chip stacking, then proper electrical connectivity and mechanical stability are achieved, but the process cycle time increases
Solution Approach 1:
Multiple sequential processes (gap-filling and planarization for each chip level) are merged into fewer processes performed after wafer-level bonding. Since the wafer provides a flat, pre-planarized surface with chips already positioned, the number of intermediate gap-filling and planarization steps is reduced, maintaining electrical connectivity reliability while significantly shortening the overall process cycle time.
Solution Approach 2:
The wafer provides preliminary planarization and chip positioning before the bonding process. Chips are pre-arranged on a flat wafer surface with proper spacing, eliminating the need for extensive post-bonding planarization work. This preliminary preparation reduces the number of subsequent processing steps required to achieve proper electrical connectivity and mechanical stability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enhances manufacturing efficiency and reduces costs by eliminating the need for individual chip placement, improving throughput, and maintaining high yield by using mature technology for wafers and newer technology for chips, while ensuring effective electrical connectivity.
Implementation Method 1
bonding a first wafer to a first carrier... bonding a second carrier onto the first plurality of chips
Data Source
AI summary
In a method, a wafer is bonded to a first carrier. The wafer includes a semiconductor substrate, and a first plurality of through-vias extending into the semiconductor substrate. The method further includes bonding a plurality of chips over the wafer, with gaps located between the plurality of chips, performing a gap-filling process to form gap-filling regions in the gaps, bonding a second carrier onto the plurality of chips and the gap-filling regions, de-bonding the first carrier from the wafer, and forming electrical connectors electrically connecting to conductive features in the wafer. The electrical connectors are electrically connected to the plurality of chips through the first plurality of through-vias.