Wafer Level Clip Array for Chip Scale Package
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Solution Overview
Problem
Current semiconductor chip encapsulation methods require cutting wafers into individual chips, followed by complex packaging procedures, which increase size and cost, making them unsuitable for miniaturization and low-cost handheld electronic device applications.
Innovation Solution
A wafer level chip scale package using a wafer size clip array, where clips connect top electrodes to down set connecting bars, and a molding material encapsulates the chip and clip, allowing for thinning and singulation of chips while reducing substrate thickness and manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional single chip encapsulation method is used, then each semiconductor element can be individually packaged, but the encapsulation size increases and manufacturing cost increases
Solution Approach 1:
The patent combines multiple semiconductor chips into a single encapsulation unit, processing multiple chips simultaneously through the encapsulation process. This merging approach reduces the total number of encapsulation operations needed, thereby decreasing overall encapsulation size and lowering manufacturing costs while maintaining individual chip functionality.
Solution Approach 2:
The patent segments the encapsulation process into modular units where groups of chips are packaged together in standardized configurations. This segmentation allows for efficient batch processing and standardized manufacturing procedures, reducing both the complexity of individual encapsulation operations and the overall manufacturing cost.
2Productivity
If wafer is cut into individual chips first, then each chip is packaged separately, but the manufacturing procedures become complex and production efficiency decreases
Solution Approach 1:
The patent performs preliminary actions by maintaining chips in their wafer-form configuration during the encapsulation process. Instead of cutting wafers into individual chips before packaging, the encapsulation is performed on the wafer level first, then the encapsulated wafer is subsequently divided. This preliminary encapsulation approach simplifies manufacturing procedures and significantly increases production efficiency.
Solution Approach 2:
The patent inverts the traditional manufacturing sequence by performing encapsulation before chip singulation. Instead of the conventional approach of cutting chips first and then packaging them individually, the method encapsulates multiple chips together in wafer form and then separates them, thereby simplifying the overall manufacturing process and improving productivity.
3Reliability
If multiple manufacturing steps are used for individual chip encapsulation, then each chip can be properly packaged, but the production time increases and cost increases
Solution Approach 1:
The patent merges multiple chip packaging operations into a single simultaneous process. By encapsulating multiple chips together in one operation rather than processing each chip separately through multiple steps, the method maintains packaging quality while dramatically reducing the total production time and associated costs.
Data Source
AI summary
A method for wafer level chip scale package comprises providing a wafer with semiconductor chips formed thereon, forming a groove alongside each chip, providing a wafer size clip array with a plurality of clip contact areas each extending to a down set connecting bar, connecting the plurality of clip contact areas to a plurality of the electrodes disposed on a top surface of the chips with down set connecting bars disposed inside the grooves, encapsulating top of wafer in molding compound, thinning the bottom portion of the wafer and dicing the thin wafer into single chip packages. The chip has source and gate electrodes on a top surface connected to a first and second clip contact areas extending to a first a second down set connecting bars respectively, with the bottom surfaces of the down set connecting bars substantially coplanar to a drain electrode located at the chip bottom surface.