Wafer-Level CMOS Image Package with TSVs for Compact Low-Power Imaging
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Solution Overview
Problem
Conventional image acquisition and processing systems are complex and power-intensive due to separate chips and modules for image acquisition, processing, coding, and control, making them unsuitable for microelectronics and wearable applications.
Innovation Solution
A microminiature image acquisition and processing system package integrates a CMOS chip with an image processor, coder, and master controller, using a wafer Re-Distribution Layer and molding layer to create a compact, low-power system with through-silicon via and adhesive film connections, reducing system size and complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a master control SOC chip system integrates an ISP and a coder to simplify the system, then the system complexity is reduced, but the package size increases and power consumption becomes high
Solution Approach 1:
The patent divides the image acquisition and processing system into separate functional modules: an image sensor chip for image acquisition, an ISP chip for image processing, and a coder chip for compression. Each module is independently packaged and then interconnected through a package-level interconnection structure, allowing the system to achieve functional integration without requiring a single large SOC chip
Solution Approach 2:
The patent transitions from planar integration (2D SOC chip layout) to three-dimensional package-level integration. By stacking multiple chips vertically and using through-silicon vias (TSVs) for interconnection, the system achieves high integration density without increasing the package footprint, effectively moving the integration solution to another dimension
2Device complexity
If a master control SOC chip system integrates an ISP and a coder to simplify the system, then the system complexity is reduced, but the power consumption increases
Solution Approach 1:
By segmenting the system into separate specialized chips (image sensor, ISP, coder), each chip can be optimized for its specific function with minimal power consumption. The image sensor chip processes only raw pixel data, the ISP chip handles only image processing tasks, and the coder chip handles compression, avoiding the overhead of a general-purpose SOC that would consume more power
Solution Approach 2:
Each chip in the segmented architecture performs its specific function autonomously and efficiently. The image sensor chip independently captures images, the ISP chip independently processes them, and the coder chip independently compresses the data, with each module serving itself for its designated task without requiring a centralized control overhead that would increase power consumption
3Adaptability or versatility
If image sensors are packaged in an independent chip package, then the image sensor can be optimized independently, but the entire system becomes complex
Solution Approach 1:
The patent merges multiple independently optimized chips (image sensor, ISP, coder) into a single package unit with integrated interconnections. The independent chips retain their individual optimization benefits while the package-level integration provides a unified system interface, reducing the complexity of managing separate packages and their interconnections
4Adaptability or versatility
If separate chips and modules are used for image acquisition, processing, coding, and control, then each module can be optimized independently, but the system size increases
Solution Approach 1:
The system is segmented into functionally optimized modules that are then integrated at the package level, achieving a balance between independent optimization and compact size
Solution Approach 2:
The patent uses three-dimensional package stacking with vertical interconnections to integrate multiple functionally optimized modules into a compact footprint, transitioning from horizontal expansion to vertical integration
Data Source
AI summary
The present invention discloses a microminiature image acquisition and processing system package structure and a preparation method thereof. This structure includes optical coated glass, a CMOS chip, a wafer Re-Distribution Layer and a molding layer, the first surface of the CMOS chip is provided with a photosensitive and microlens region and a metal bonding pad, and a through-silicon via is etched in a second surface of the CMOS chip until it extends to the metal bonding pad on the first surface; the wafer Re-Distribution Layer covers the second surface of the CMOS chip and extends to the through-silicon via. The structure and the method of the present invention are integrated with wafer-level package and SIP integrated package technologies to achieve single package of the whole device, thereby greatly reducing the system complexity and power consumption, reducing the overall product size and signal path, and improving the image anti-interference capability.