Wafer-Level Design Compliance Checking via Tile-Based Segmentation
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Solution Overview
Problem
Integrated circuit designs with multiple interconnected chips face significant computational challenges in checking for antenna rule compliance, as existing methods require full rule validation across combined large layouts, leading to inefficiencies and potential damage from plasma-induced charge buildup.
Innovation Solution
A method and system that utilize a tile-based approach to check compliance along chip peripheries, determining a tile area that crosses chip boundaries and modifies non-compliant regions to ensure compliance, thereby reducing computational burden and preventing charge buildup-related damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If full rule validation is performed across combined large layouts of multiple chips, then antenna rule compliance is ensured, but computational cost increases dramatically
Solution Approach 1:
The patent divides the wafer-level layout into individual chip layout portions and focuses compliance checking only on periphery regions where chips intersect with tile areas. This segmentation avoids the need to perform full rule validation across the entire combined layout, significantly reducing computational cost while maintaining reliability by checking all critical periphery regions where antenna rules could be violated.
2Measurement precision
If tile area size is increased to cover more chip periphery, then compliance checking coverage is improved, but computational resources increase
Solution Approach 1:
The patent applies local quality by determining tile areas with specific sizes that cross chip layout boundaries and focusing compliance checking only on periphery regions within these tiles. Each tile is sized to cover the necessary periphery area where antenna rules could be violated, providing adequate coverage without unnecessarily increasing computational resources by checking the entire chip area.
Data Source
AI summary
Methods and systems for checking a wafer-level design for compliance with a rule include determining a tile area, having a size that is based on the one or more layout design rules, that crosses a boundary between adjacent chip layouts and that leaves at least a portion of each chip layout uncovered. It is determined that a portion of a first chip layout inside the tile area fails to comply with one or more layout design rules. The first chip layout is modified, responsive to the determination that the first chip layout within the tile area fails to comply with the one or more layout design rules, to bring non-compliant periphery chip regions into compliance. It is determined that the portion of the first chip layout within the tile area complies with the one or more design rules after modifying the first chip layout. A multi-chip wafer is fabricated that includes the chip layouts.