Wafer-Level Die Bridge RDL Formation for High-Yield Interconnects
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing semiconductor manufacturing processes for forming bridges between chips are complex and limited, often requiring foundry assistance, leading to increased costs and low yields due to the challenges of forming redistribution layers (RDLs) after chip placement, which can result in the discard of expensive chips.
Innovation Solution
A method and apparatus for forming a wafer-level die bridge by first creating a redistribution layer on a carrier, affixing a bridge die with electrical connections, and coupling dies to the RDL and bridge die using mold layers and interconnects, allowing for precise control and higher yields without the need for foundry assistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bridges are formed in substrates using foundry processes, then electrical connections between chips are achieved, but manufacturing complexity increases and limits production to foundries only
Solution Approach 1:
The patent applies preliminary action by forming the redistribution layer (RDL) on the carrier substrate before placing the chips and bridges. This sequence allows the RDL to be prepared in advance with proper alignment features, simplifying subsequent chip placement and interconnection. The RDL is formed with conductive traces and vias that pre-establish the electrical connection paths before the actual die assembly occurs.
Solution Approach 2:
The patent uses an intermediary approach by introducing a carrier substrate as a temporary platform for assembling the complete die bridge structure. The carrier holds the RDL, bridges, and chips together during assembly and processing, then is removed after bonding. This intermediary carrier simplifies the manufacturing process by providing a stable workspace and enabling OSAT facilities to perform the assembly without complex foundry equipment.
2Reliability
If redistribution layers are formed after bridge and chip placement, then chip connections are established, but RDL yields are low causing expensive chips to be discarded
Solution Approach 1:
The patent resolves this contradiction by performing the RDL formation step before chip placement. The redistribution layer is created on the carrier substrate with precise conductive traces and vias established in advance. This preliminary formation allows for proper alignment features to be incorporated, ensuring high yield when chips are subsequently placed and connected to the pre-formed RDL structure.
3Manufacturing precision
If foundry processes are used for die bridge formation, then precise electrical connections are achieved, but Outsourced Assembly and Test facilities cannot perform the process internally
Solution Approach 1:
The patent enables OSAT facility accessibility by using a carrier substrate as an intermediary platform that simplifies the manufacturing process. The carrier provides a stable base for forming the RDL and assembling the die bridge structure using standard OSAT equipment. After assembly, the carrier is removed and the complete structure is transferred to the final substrate, achieving precise electrical connections without requiring specialized foundry processes throughout.
Solution Approach 2:
The patent applies segmentation by dividing the manufacturing process into distinct stages: RDL formation on carrier, chip and bridge placement on carrier, carrier removal, and final assembly on substrate. This segmentation allows OSAT facilities to perform the intermediate assembly steps with their existing equipment, while the final precision connection steps are completed after carrier removal, making the overall process accessible to outsourced facilities.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces manufacturing complexity, increases RDL yields, and allows Outsourced Assembly and Test facilities to perform the process internally, reducing costs and enabling compatibility with larger packages by eliminating the need for interposers and improving fine pitch control.
Implementation Method 1
affixing a bridge die on the RDL using an adhesive between the bridge die and the RDL
Implementation Method 2
forming at least one electrical interconnect on the RDL or at least one electrical interconnect on the bridge die; forming the at least one TMV using an electroplating process
Implementation Method 3
forming a first mold layer over the RDL and the bridge die; forming a second mold layer on the first mold layer and on the plurality of dies
Data Source
AI summary
A wafer-level bridge die is affixed with an adhesive layer to a redistribution layer (RDL) that has been temporarily bonded to a carrier. Electrical interconnects are formed on the RDL and on the bridge die and encapsulated in a first mold layer. A plurality of dies are coupled to the RDL and the bridge die such that a die is electrically connected to at least one electrical interconnect of the RDL and to at least one electrical interconnect of the bridge die. A second mold layer is formed on the first mold layer to encapsulate the plurality of dies. The temporary bond is then broken and the carrier is removed, exposing the RDL connections.