Wafer Level Die Integration Using Redistribution Layers
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor manufacturing methods face challenges in reducing the area required for interconnects between semiconductor dies in wafer level chip scale packages, as through hole conductive vias are difficult to form and require significant die space.
Innovation Solution
The method involves mounting a second semiconductor die over a first semiconductor die, forming an insulating layer, and creating a conductive layer to electrically connect contact pads, with redistribution layers and solder bumps providing inter-level interconnects without using through hole vias, thereby reducing the space needed for interconnects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If through hole conductive vias are used for interconnect between semiconductor die, then electrical connection is achieved, but die area is significantly consumed and manufacturing complexity increases
Solution Approach 1:
The patent transitions from planar through-hole vias to three-dimensional bump interconnects. Solder bumps are formed on the surface of the die and extend vertically to connect with redistribution layers, utilizing the vertical dimension rather than requiring lateral space through holes in the die substrate.
Solution Approach 2:
The patent extracts the conductive path from the die substrate itself (through-hole vias) and relocates it to the die surface (solder bumps). This separates the interconnect function from the die structure, allowing the die area to be preserved while achieving electrical connection through surface-mounted bumps.
2Reliability
If through hole conductive vias are used for interconnect, then electrical connection is established, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The interconnect structure is segmented into distinct functional layers: solder bumps for mechanical and electrical connection, redistribution layers for signal routing, and insulation layers for electrical isolation. This segmentation simplifies manufacturing by allowing each layer to be formed and processed independently rather than requiring complex through-hole formation.
Solution Approach 2:
The patent employs multiple vertical layers (z-dimension) including bottom redistribution layers, middle redistribution layers, and top redistribution layers stacked above the die surface. This vertical stacking achieves complex interconnect functionality without increasing lateral complexity or requiring through-hole structures.
3Ease of manufacture
If larger area is allocated for interconnect, then through hole vias can be formed, but signal propagation delay and capacitance increase
Solution Approach 1:
By moving interconnects to the vertical dimension with thin redistribution layers and compact bump structures, the lateral distance for signal propagation is minimized. The short vertical paths through the bump and redistribution layers reduce signal delay and capacitance compared to lateral through-hole routes.
Solution Approach 2:
The patent uses fine-pitch solder bumps with small diameters (e.g., 50-100 micrometers) and thin redistribution layer configurations to reduce the physical dimensions of the interconnect path. These parameter changes decrease both the area occupied and the signal propagation distance, improving speed while maintaining manufacturability.
Data Source
AI summary
In a wafer level chip scale package (WLCSP), a semiconductor die has active circuits and contact pads formed on its active surface. A second semiconductor die is disposed over the first semiconductor die. A first redistribution layer (RDL) electrically connects the first and second semiconductor die. A third semiconductor die is disposed over the second semiconductor die. The second and third semiconductor die are attached with an adhesive. A second RDL electrically connects the first, second, and third semiconductor die. The second RDL can be a bond wire. Passivation layers isolate the RDLs and second and third semiconductor die. A plurality of solder bumps is formed on a surface of the WLCSP. The solder bumps are formed on under bump metallization which electrically connects to the RDLs. The solder bumps electrically connect to the first, second, or third semiconductor die through the first and second RDLs.