Wafer Level Die Package Structure for High Pin Density
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Solution Overview
Problem
The miniaturization and functional diversification of semiconductor dice lead to increased pin density, making traditional packaging challenging and reducing yield, while existing wafer level package technologies have limitations in cost, production cycle, and heat dissipation for large-scale IC chips like NAND and NOR flash memory.
Innovation Solution
A die packaged structure is developed using a wafer level packaging process with simple wire bonding, where a packaged substrate with exposed pads and external connecting terminals is aligned with the die, allowing for efficient electrical connection and heat dissipation through a combination of metal wires and a packaged body, enabling cost-effective and scalable packaging.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional packaging methods are used for miniaturized semiconductor dies with increased pin density, then the die can be packaged, but the packaging difficulty increases and yield decreases
Solution Approach 1:
The patent applies preliminary action by performing wafer-level packaging before the wafer is cut into individual dies. The packaged substrate is prepared in advance with connection terminals and adhesive layers, and the entire wafer is packaged simultaneously rather than handling each die separately. This reduces packaging complexity and improves yield while maintaining precision for miniaturized dies with high pin density.
2Productivity
If wafer level package technology is used, then production cycle is shortened and cost is reduced, but heat dissipation performance is insufficient for large-scale IC chips
Solution Approach 1:
The patent segments the packaging structure into distinct functional layers: a packaged substrate with connection terminals, an adhesive layer for thermal and electrical connection, and the semiconductor wafer. This segmentation allows the packaged substrate to serve as a dedicated heat dissipation pathway while maintaining the productivity benefits of wafer-level processing. The adhesive layer specifically facilitates thermal conduction from the die to the packaged substrate.
Solution Approach 2:
The patent introduces an adhesive layer as an intermediary between the semiconductor die and the packaged substrate. This intermediary layer serves dual functions: electrical connection through conductive adhesive and thermal conduction for heat dissipation. This resolves the contradiction by enabling effective heat transfer while maintaining the simplified wafer-level packaging process.
3Adaptability or versatility
If more pads are placed in the central region of the die to increase pin density, then the functionality increases, but the packaging difficulty increases
Solution Approach 1:
The patent redistributes connection terminals from a two-dimensional planar arrangement to a three-dimensional configuration on the packaged substrate. The packaged substrate provides additional spatial dimensions and vertical layering for connection terminals, allowing high-density pads on the die to be mapped to a more manageable terminal arrangement on the substrate. This dimensional transition simplifies the packaging process while supporting functional diversity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution achieves a cost-effective, scalable die packaged structure with improved heat dissipation and electrical connectivity, suitable for large-scale IC chips, enhancing the packaging efficiency and reducing production costs.
Implementation Method 1
the back surface of the packaged substrate is fixed on the die by an adhesive layer
Implementation Method 2
a plurality of connecting terminals is electrically connected with the plurality of external connecting terminals by a plurality of first metal wires
Implementation Method 3
A packaged body is encapsulated the packaged substrate, the die and the plurality of second metal wires
Data Source
AI summary
A die packaged structure includes a pad on the central region of the die. A packaged substrate with an opening disposed in the central region, and a connecting terminal is passed through the packaged substrate and disposed around the opening. An external connecting terminal is disposed on the four sides of the packaged substrate. A first metal wire is electrically connected the connecting terminal with the external connecting terminal, and the back of the packaged substrate is fixed on the die, such that the pad is exposed on the opening. A second metal wire is electrically connected the pad with the connecting terminal. A packaged body is encapsulated the packaged substrate, the die and the second metal wire, and the external connecting terminal is exposed. A conductive component is electrically connected with the external connecting terminal and is arranged on the four sides of the die packaged structure.