Wafer Level Integration Package With Through-Hole Interconnections
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Solution Overview
Problem
The challenge is to achieve higher integration of semiconductor devices with differing functionality while maintaining or reducing the package profile, as greater integration often results in larger or thicker packages, compromising miniaturization.
Innovation Solution
A semiconductor package design featuring a substrate with a top contact pad, through-hole interconnections, and an encapsulant that covers the side of the substrate, allowing for efficient mounting and electrical connection of dies, while maintaining a smaller size through the use of conductive vias and encapsulants to support both top and bottom surface components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If greater integration is achieved using multiple dies and components, then functionality and circuit density are improved, but package footprint or thickness increases
Solution Approach 1:
The patent transitions from planar integration to three-dimensional integration by stacking multiple dies vertically. Through-hole interconnections penetrate the substrate to electrically connect dies on opposite sides, enabling functional integration without increasing package footprint. The substrate acts as an interposer that routes signals between stacked dies, achieving higher functionality density in a compact vertical arrangement.
2Adaptability or versatility
If greater integration is achieved using multiple dies and components, then functionality and circuit density are improved, but package thickness increases
Solution Approach 1:
The patent embeds multiple functional dies within a compact vertical structure. Smaller dies are stacked and nested within the package volume, with the substrate providing structural support and electrical interconnection. This nesting approach maximizes the use of available package volume while maintaining a compact profile, as each die contributes functionality without requiring lateral expansion.
3Reliability
If through-hole interconnections are used to connect stacked dies, then electrical connectivity between dies is improved, but manufacturing complexity increases
Solution Approach 1:
The through-hole interconnections are formed in the substrate before die attachment. This preliminary formation of conductive pathways allows subsequent die stacking to proceed more efficiently, as the electrical connection architecture is already in place. The substrate is prepared with through-holes and conductive material deposited beforehand, enabling streamlined assembly of the stacked die structure.
Data Source
AI summary
A semiconductor package has a first conductive layer formed on a top surface of a substrate. A conductive via is formed between the first conductive layer and a bottom surface of the substrate. A semiconductor component is mounted to the substrate and electrically connected to the first electrical contact pad. The semiconductor component can be a flip chip semiconductor device, wire bond semiconductor device, or passive component. An encapsulant is deposited over the semiconductor component. The encapsulant extends into a channel formed on a side of the substrate from the top surface to the bottom surface of the substrate. An interconnect structure is formed over the bottom surface of the substrate. A heat spreader structure can be disposed over the semiconductor component. An EMI shield can be disposed over the semiconductor component. A plurality of semiconductor components can be stacked in a package-in-package arrangement.