Wafer Level Interconnect Structure Using Sacrificial Substrate
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Solution Overview
Problem
The existing methods for wafer level package integration face challenges due to the low glass transition temperature of organic substrates, which limits processing options and increases inter-wafer and intra-wafer registration variation, reducing manufacturability and wafer integration.
Innovation Solution
A method for forming a wafer level chip scale package involves creating a wafer level interconnect structure on a substrate with temperatures exceeding 200°C, using multiple passivation and conductive layers, and mounting semiconductor die in electrical contact, followed by encapsulation and removal of the substrate to form solder bumps and under bump metallization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If organic substrate with low glass transition temperature is used for forming interconnect structure, then ease of manufacture is improved, but processing temperature options are limited and registration precision deteriorates
Solution Approach 1:
The patent changes the substrate material from organic to inorganic, fundamentally altering the temperature parameter range available for processing. This enables high-temperature processing (exceeding 200°C) that was previously impossible with organic substrates, thereby improving registration precision while maintaining ease of manufacture through the new material class
Solution Approach 2:
The patent employs a sacrificial substrate approach where a temporary substrate is used during processing and then removed. This disposable substrate enables complex interconnect formation with multiple passivation and conductive layers, after which the substrate is eliminated, leaving only the functional interconnect structure on the final device
2Manufacturing precision
If high temperature processing is applied to form interconnect structure, then registration precision is improved, but substrate material options are limited due to glass transition temperature
Solution Approach 1:
The patent changes the substrate material from organic to inorganic, fundamentally altering the temperature parameter range available for processing. This enables high-temperature processing (exceeding 200°C) that was previously impossible with organic substrates, thereby improving registration precision while maintaining ease of manufacture through the new material class
Solution Approach 2:
The patent uses an inorganic substrate as an intermediary platform that can withstand high processing temperatures. This mediator substrate enables the formation of high-temperature interconnect structures, which are then transferred or integrated with the semiconductor die, allowing the temporary use of temperature-resistant materials without requiring the final product to contain them
3Adaptability or versatility
If multiple passivation and conductive layers are formed for wafer level interconnect, then interconnect functionality is improved, but device complexity increases
Solution Approach 1:
The patent combines multiple interconnect functions into a single integrated wafer-level structure. By forming multiple passivation and conductive layers simultaneously on the substrate before die attachment, the patent merges what would otherwise require separate packaging steps into one unified process, improving functionality while managing complexity through integration
Solution Approach 2:
The patent performs preliminary formation of the complete multi-layer interconnect structure on the substrate before attaching the semiconductor die. This preliminary action allows complex interconnect architectures to be established in advance, simplifying the subsequent die attachment process and enabling sophisticated routing patterns without increasing the complexity of the final assembly steps
Data Source
AI summary
In a wafer level chip scale package, a wafer level interconnect structure is formed on a dummy substrate with temperatures in excess of 200° C. First semiconductor die are mounted on the wafer level interconnect structure. The wafer level interconnect structure provides a complete electrical interconnect between the semiconductor die and one or more of the solder bumps according to the function of the semiconductor device. A second semiconductor die can be mounted to the first semiconductor die. A first encapsulant is formed over the semiconductor die. A second encapsulant is formed over the first encapsulant. The dummy substrate is removed. A first UBM is formed in electrical contact with the first conductive layer. Solder bumps are made in electrical contact with the first UBM. A second UBM is formed to electrically connect the semiconductor die to the wafer level interconnect structure.