Wafer-Level LED Package Layout for Heat and Current Spreading
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Solution Overview
Problem
The existing light emitting diode (LED) package manufacturing process is complex, leading to potential defects and high costs, with limitations in size, optical properties, and heat/current spreading, especially for large-area chips, and is prone to light scattering without phosphor conversion.
Innovation Solution
A wafer-level LED package is developed with a process that integrates semiconductor layers, bumps, and protective layers on a substrate, facilitating packaging during chip manufacturing, reducing light scattering, and enhancing heat dissipation and current spreading.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If light emitting diode chips are manufactured separately and then packaged, then the packaging process can be optimized, but the overall manufacturing process becomes complicated and costly
Solution Approach 1:
The patent merges the chip manufacturing process and packaging process into a single integrated wafer-level process. The LED chips are fabricated and packaged simultaneously on the growth substrate without separation, eliminating the need for separate chip mounting steps and reducing overall process complexity while maintaining packaging optimization benefits
2Ease of manufacture
If light emitting diode chips are manufactured separately and then packaged, then the packaging can be optimized, but the manufacturing costs increase
Solution Approach 1:
The patent combines chip fabrication and packaging into a single wafer-level process, eliminating multiple separate manufacturing steps including chip mounting, wire bonding, and encapsulation. This integration reduces the total number of process steps, decreases manufacturing time, and lowers overall production costs while maintaining optimized packaging structure
3Temperature
If the light emitting diode package size is increased to accommodate larger chips, then heat dissipation and current spreading improve, but the package becomes too large for mobile applications
Solution Approach 1:
The patent transitions from traditional three-dimensional packaging with separate mounting steps to a planar wafer-level integration approach. By maintaining the chip and package in the same plane during fabrication, the design achieves improved heat dissipation and current spreading without increasing vertical or lateral package dimensions, making it suitable for mobile applications
4Device complexity
If light is emitted from the side of the package without phosphor conversion, then the structure is simplified, but optical properties deteriorate
Solution Approach 1:
The patent introduces a phosphor layer as an intermediary component between the LED chip and the external environment. This phosphor layer converts the emitted light to achieve desired optical properties while maintaining the simplified side-emitting package structure, thus resolving the conflict between structural simplicity and optical performance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the manufacturing process, reduces defects and costs, enables smaller and larger LED packages, and improves optical efficiency by minimizing light scattering and enhancing heat and current management.
Implementation Method 1
The electrons moving toward the PN junction part are coupled with the holes. The electrons move from a conduction band to a valence band. In this case, energy corresponding to a height difference between the conduction band and the valence band, that is, the energy difference is emitted. The energy is emitted in a form of light.
Implementation Method 2
the light emitting diode package according to the related art may emit light scattered without being converted by a phosphor layer from a side thereof
Data Source
AI summary
A light emitting diode, including a first type semiconductor layer, an active layer, and a second type semiconductor layer; an ohmic contact layer disposed on the second type semiconductor layer; a first insulating layer disposed on the semiconductor structure and including a first opening overlapping the first type semiconductor layer and a second opening overlapping the ohmic contact layer; a first connection wiring disposed on the first insulating layer, the first connection wiring having a first portion and a second portion; and a second connection wiring disposed on the first insulating layer and spaced apart from the first connection wiring, the second connection wiring electrically connected to the second type semiconductor layer through the second opening. The second connection wiring surrounds at least a portion of the first portion of the first connection wiring in a plan view.