Wafer-Level Optical IC Testing via Bypass Waveguide

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Solution Overview

Problem

Conventional methods for testing optical IC chips after dicing require individual alignment of optical fibers, increasing testing time and effort, and fail to allow optical circuit testing in the wafer state before dicing due to non-connected optical waveguides at the terrace where semiconductor optical amplifiers are mounted.

Innovation Solution

An optical device with a testing optical waveguide that bypasses the non-connected optical waveguide portion at the terrace, enabling test light to be guided to the optical circuit via grating couplers arranged outside the optical IC chip region on the wafer, allowing testing of optical circuits before dicing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If optical fiber alignment is performed individually for each optical IC chip after dicing, then testing accuracy is maintained, but testing time and operator labor increase significantly

Engineering Contradiction:
Improvetesting accuracyVSAvoidtesting throughput
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The patent performs optical circuit testing in the wafer state before dicing into individual IC chips. By conducting tests preliminarily when multiple chips are still integrated on the wafer substrate, the system enables simultaneous testing of multiple chips without requiring individual fiber alignment for each chip, thus maintaining accuracy while improving throughput

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent combines multiple optical IC chips into a single wafer-level testing unit. By merging the testing process for multiple chips into one unified operation using a single optical fiber, the system eliminates the need for repeated alignment procedures, thereby significantly reducing testing time and operator labor while maintaining measurement precision

Inventive Principle:
Principle #5Merging (Combining)

2Productivity

If optical waveguides are connected through the terrace for mounting optical chip components, then the optical circuit can be tested in wafer state, but the terrace structure creates non-connected portions that block light transmission

Engineering Contradiction:
Improvewafer-state testing capabilityVSAvoidoptical waveguide connectivity
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent segments the optical waveguide into two separate portions: a first optical waveguide that extends from the grating coupler to the terrace, and a second optical waveguide that extends from the terrace to the optical circuit. This segmentation allows each waveguide portion to be independently optimized and connected, bypassing the non-connected terrace region while maintaining overall optical connectivity for wafer-state testing

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces an intermediary optical coupling structure that bridges the first and second optical waveguides. This intermediary mechanism enables light transmission between the waveguide portions that would otherwise be blocked by the terrace, ensuring reliable optical connectivity while allowing the terrace to remain available for mounting optical chip components

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces operator labor and testing time by enabling simultaneous testing of multiple optical IC chips in the wafer state before dicing, improving throughput and allowing for efficient integration and reduction in element size using silicon substrates.

Implementation Method 1

a grating coupler (GC) is disposed in a portion of the wafer other than the region of the optical IC chip to be measured, whereby an optical signal is input to the optical circuit via the optical waveguide extending beyond the dicing line

Methodology Applied
Scientific EffectGrating coupler: Diffraction Grating

Implementation Method 2

a testing optical waveguide that guides test light to the optical circuit to be tested, by bypassing a non-connected optical waveguide portion at a terrace for mounting an optical chip component

Methodology Applied
Scientific EffectOptical waveguide: Waveguide (optics)

Data Source

PatentUS11604116B2Optical device having terrace for mounting optical chip component and method of testing optical device having terrace for mounting optical chip component
Publication Date: 2023.03.14 FUJITSU OPTICAL COMPONENTS LTD
  • US11604116B2 patent drawing
  • US11604116B2 patent drawing
  • US11604116B2 patent drawing

AI summary

An optical device cut from a wafer into a chip by dicing, on the wafer, the optical device includes a plurality of optical waveguides; an optical circuit connected to the optical waveguide; and of the plurality of optical waveguides, a testing optical waveguide that guides test light to the optical circuit to be tested, by bypassing a non-connected optical waveguide portion at a terrace for mounting an optical chip component.