Wafer Level Package Reinforcement Zig for Warpage Control
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Solution Overview
Problem
The warpage and chip shift phenomena pose challenges in fabricating reliable fan-out wafer level packages (FOWLPs), which are essential for producing compact and reliable semiconductor devices without printed circuit boards.
Innovation Solution
A wafer level package design that includes semiconductor chips attached to a carrier with a reinforcement zig structure, where a molded layer covers and embeds the reinforcement zig, providing additional adhesive strength and preventing chip movement during the molding process, thus addressing warpage and chip shift issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If semiconductor chips are attached to a carrier for FOWLP fabrication, then chip density and integration are improved, but warpage and chip shift phenomena occur during molding
Solution Approach 1:
The reinforcement zig structure is attached to the carrier before the semiconductor chips are mounted. This preliminary placement of the reinforcement structure prepares the substrate to resist warpage forces before molding occurs, preventing both warpage and chip shift during the subsequent molding process
Solution Approach 2:
The reinforcement zig structure serves as a composite element combining the carrier substrate with an additional reinforcement layer. This composite structure provides enhanced mechanical strength and dimensional stability, allowing high chip density while maintaining fabrication reliability by resisting warpage during molding
2Volume of moving object
If chip size is reduced to enable compact mobile products, then device compactness is improved, but adhesive strength between chip and carrier becomes insufficient
Solution Approach 1:
Instead of relying solely on the limited bonding area of small chips, the reinforcement zig structure extends the adhesive interface into a larger peripheral region. This dimensional extension provides additional bonding area and distributes mechanical stresses, enhancing adhesive strength while maintaining small chip size for compact devices
3Ease of manufacture
If standardized ball layout is used to simplify PCB design, then manufacturing ease is improved, but chip stability during molding deteriorates due to warpage
Solution Approach 1:
The reinforcement zig structure is installed before chip mounting and molding to preemptively counteract warpage forces. This preliminary reinforcement ensures chip stability throughout the molding process while allowing the use of standardized ball layouts that simplify manufacturing and PCB design
Data Source
AI summary
A wafer level package and or a semiconductor device unit may be provided. The wafer level package may include semiconductor chips disposed on an interconnection structure layer and laterally spaced apart from each other. The wafer level package may include a reinforcement zig attached to the semiconductor chips. The wafer level package may include a molded layer covering the semiconductor chips and embedding the reinforcement zig. Related methods are also provided.