Wafer-Level Semiconductor Packaging with BCB Lithography
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Solution Overview
Problem
Traditional wafer-level packaging methods are complex, costly, and offer inadequate environmental protection, with issues such as high-temperature thermal bonding, adhesive outgassing, and large cavities that compromise mechanical and environmental protection, and existing methods often degrade device performance due to direct dielectric film deposition on transistors.
Innovation Solution
A method involving lithographic processing of BCB material to form device-exposing openings and a rigid dielectric layer, allowing for precise patterning and bonding without impacting transistor performance, with a support structure for easy alignment and removal, creating air cavities that minimize the impact of applied coatings and enable direct wire bond connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If thermal bonding is used to bond wafers, then bonding strength is improved, but processing temperature becomes excessively high (in excess of 400 C)
Solution Approach 1:
The patent changes the bonding parameter from thermal bonding (high temperature) to adhesive bonding (lower temperature), resolving the contradiction between achieving sufficient bonding strength and avoiding excessively high processing temperatures that could damage semiconductor devices
2Temperature
If adhesive bonding is used to bond wafers, then processing temperature is reduced, but adhesive outgassing occurs
Solution Approach 1:
The patent uses a sacrificial layer (suspension layer) that is temporarily present during bonding but is subsequently removed. This disposable layer enables adhesive bonding at lower temperatures while preventing outgassing issues by providing a controlled interface that can be cleanly removed after bonding
3Ease of manufacture
If large cavities are used to cover entire chip, then alignment difficulty is reduced, but mechanical strength and environmental protection are compromised
Solution Approach 1:
The patent implements local quality by creating cavities of appropriate size only over active devices rather than covering the entire chip. The suspension layer provides local support precisely where needed, enabling smaller, mechanically stronger cavities that still achieve proper alignment and coverage of critical components
4Device complexity
If direct dielectric film deposition is performed on transistors, then packaging process is simplified, but device performance is degraded
Solution Approach 1:
The patent segments the packaging structure by introducing a suspension layer that separates the dielectric film from the transistor active areas. This segmentation allows the dielectric film to be deposited over cavities without directly contacting transistors, preserving device performance while maintaining packaging process efficiency
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method simplifies the packaging process, reduces mechanical and environmental risks, maintains device performance by preserving the air dielectric constant, and allows for flexible cavity design, enhancing manufacturability and protection while enabling easy assembly and connection.
Implementation Method 1
lithographic processing of BCB material to form device-exposing openings and a rigid dielectric layer
Data Source
AI summary
A method for packaging a plurality of semiconductor devices formed in a surface portion of a semiconductor wafer. The method includes: lithographically forming, in a first lithographically processable material disposed on the surface portion of the semiconductor wafer, device exposing openings to expose the devices and electrical contact pad openings to expose electrical contact pads for devices; and mounting a support having a rigid dielectric layer formed on a selected portion of the support, such rigid dielectric layer comprising a second lithographically processable material, such rigid material being suspended over the device exposing openings and removed from portions of the support disposed over the electrical contacts pads openings in the first lithographically processable material. The support is released and removed from the second lithographically processable material, leaving the second photolithographically processable material bonded to the first photolithographically processable material.