Wafer-Level Semiconductor Package with Conductive Pillar Interconnects
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Solution Overview
Problem
Existing semiconductor packaging technologies face challenges in efficiently integrating and connecting multiple semiconductor dies at the wafer level, particularly in achieving reliable electrical and thermal connections while maintaining a compact form factor.
Innovation Solution
A method involving the formation of conductive pillars embedded in the semiconductor substrate, which are used to connect semiconductor dies through through-silicon vias (TSVs) and interconnect structures, allowing for efficient electrical and thermal pathways, and a protective encapsulation to safeguard these connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple semiconductor dies are integrated at the wafer level, then productivity and device complexity are improved, but manufacturing precision and reliability of connections become more difficult to maintain
Solution Approach 1:
The patent divides the wafer into multiple individual die regions, each with its own encapsulation structure. This segmentation allows each die to be processed and connected independently while maintaining wafer-level efficiency, thereby preserving manufacturing precision despite high productivity requirements.
Solution Approach 2:
The patent introduces an encapsulation material as an intermediary substance that fills the spaces between adjacent dies and provides a controlled environment for connection formation. This intermediary enables precise alignment and connection between dies while maintaining overall wafer-level integration efficiency.
2Reliability
If conductive pillars and through-silicon vias are used for connections, then electrical and thermal pathways are improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent combines electrical and thermal connection functions into a single integrated conductive pillar structure. By merging these two functions into one component, the system achieves reliable electrical and thermal pathways without proportionally increasing device complexity.
Solution Approach 2:
The conductive pillars serve multiple functions simultaneously: they provide electrical connection between dies, serve as thermal conduction pathways, and act as structural support elements. This multi-functionality reduces overall device complexity while maintaining connection reliability.
3Reliability
If protective encapsulation is added to safeguard connections, then reliability is improved, but device volume and manufacturing steps increase
Solution Approach 1:
The patent implements a nested encapsulation structure where the encapsulation material is positioned within the inter-die spaces rather than as a separate outer layer. This nesting approach provides protective coverage for connections while minimizing the overall package volume increase.
Solution Approach 2:
The encapsulation material is applied as a thin film or flexible shell that conforms to the contours of the die structures. This thin-film approach provides adequate protection for connections without significantly increasing the package volume.
Data Source
AI summary
A semiconductor package includes a first semiconductor die, a second semiconductor die, an insulating encapsulation, and a plurality of conductive pillars. The second semiconductor die is located on and electrically communicates to the first semiconductor die through joints therebetween. The insulating encapsulation encapsulates the first semiconductor die and the second semiconductor die and covers the joints. The plurality of conductive pillars is next to and electrically connected to the first semiconductor die and the second semiconductor die, and is covered by the insulating encapsulation.