Wafer-Level Antenna Conductor Integration via Screen Printing
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Solution Overview
Problem
Conventional methods for manufacturing integrated circuit devices with antenna conductors require significant space and complex packaging processes, limiting miniaturization and increasing production costs, especially for longer distance communication applications.
Innovation Solution
The method involves integrating screen-printing techniques into the wafer-level package process to form metal bumps or antenna conductors on integrated circuit components, allowing for a multi-layer antenna structure and simplifying the manufacturing process by encapsulating components with an insulating layer and exposing metal bumps for additional antenna conductor formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If antenna conductors are directly disposed on the circuit board and integrated circuit chips are surface-mounted one-by-one, then the antenna conductor arrangement is simple, but the required space increases and the packaging process becomes highly complicated
Solution Approach 1:
The patent merges the antenna conductor formation with the integrated circuit chip manufacturing process by forming antenna conductors directly on the wafer surface during the semiconductor fabrication process, rather than separately on the circuit board. This integration eliminates the need for separate antenna conductor arrangements and reduces the overall device space requirement.
Solution Approach 2:
The patent transitions from a two-dimensional surface mounting approach to a three-dimensional integrated structure by forming antenna conductors within the wafer layer itself and using vertical interconnect structures. This dimensional change allows for more compact space utilization while maintaining manufacturing simplicity.
2Ease of manufacture
If antenna conductors are directly disposed on the circuit board and integrated circuit chips are surface-mounted one-by-one, then the antenna conductor arrangement is simple, but the packaging process becomes highly complicated
Solution Approach 1:
The patent combines the antenna conductor formation, chip fabrication, and packaging processes into a single integrated wafer-level manufacturing process. By forming antenna conductors directly on the wafer and using wafer-level packaging techniques, the separate steps of antenna conductor arrangement and chip mounting are merged, significantly reducing packaging process complexity.
Solution Approach 2:
The patent performs preliminary actions by forming antenna conductors and establishing interconnect structures during the wafer fabrication process itself, before the chips are separated and packaged. This preliminary formation of antenna conductors eliminates the need for complex post-fabrication mounting and connection operations.
3Area of stationary object
If antenna conductors are formed on the integrated circuit chip surface by semiconductor thin film technique, then the production cost increases, but the required space is reduced
Solution Approach 1:
The patent merges antenna conductor formation with the standard semiconductor fabrication process, using the same thin film deposition and patterning techniques already employed for creating circuit interconnects. This integration eliminates the need for additional specialized processing steps, thereby reducing production costs while achieving compact antenna structures.
Solution Approach 2:
The patent employs universal semiconductor manufacturing techniques that serve multiple functions: the same thin film deposition and patterning processes used for creating circuit interconnects are also used to form antenna conductors. This multi-functionality approach reduces the need for specialized equipment and processes, thereby lowering production costs.
4Device complexity
If antenna conductors are formed on the integrated circuit chip surface, then the manufacturing process becomes simpler, but the communication distance is limited to short distance
Solution Approach 1:
The patent extends antenna functionality to longer distances by creating three-dimensional multi-layer antenna structures within the wafer, rather than relying solely on two-dimensional surface patterns. By utilizing vertical stacking and inter-layer connections, the effective antenna length is increased without proportionally increasing the chip footprint, thereby extending communication range while maintaining manufacturing simplicity.
Data Source
AI summary
A method for manufacturing an integrated circuit device having antenna conductors is provided. The method includes the steps of providing a wafer with a plurality of integrated circuit components; forming a first antenna conductor on the surface of each integrated circuit component; forming a plurality of metal bumps above the first antenna conductor; coating an insulating layer to encapsulate the plurality of integrated circuit components and to cover the plurality of metal bumps; removing a portion of the insulating layer to expose a top portion of each metal bump; and forming a second antenna conductor on the insulating layer by screen printing.